From 735738c7b618be2c0d30fc072016894c54281c9b Mon Sep 17 00:00:00 2001 From: MerryMage Date: Sat, 4 Jul 2020 10:17:50 +0100 Subject: [PATCH] A32: Implement ASIMD VPMAX, VPMIN (floating-point) --- src/frontend/A32/decoder/asimd.inc | 2 ++ .../A32/translate/impl/asimd_three_regs.cpp | 22 +++++++++++++++++++ .../A32/translate/impl/translate_arm.h | 2 ++ 3 files changed, 26 insertions(+) diff --git a/src/frontend/A32/decoder/asimd.inc b/src/frontend/A32/decoder/asimd.inc index 60179bce..05a95be2 100644 --- a/src/frontend/A32/decoder/asimd.inc +++ b/src/frontend/A32/decoder/asimd.inc @@ -46,6 +46,8 @@ INST(asimd_VCGT_reg_float, "VCGT (register)", "111100110D1znnnndddd111 INST(asimd_VACGE, "VACGE", "111100110Doznnnndddd1110NQM1mmmm") // ASIMD INST(asimd_VMAX_float, "VMAX (floating-point)", "111100100D0znnnndddd1111NQM0mmmm") // ASIMD INST(asimd_VMIN_float, "VMIN (floating-point)", "111100100D1znnnndddd1111NQM0mmmm") // ASIMD +INST(asimd_VPMAX_float, "VPMAX (floating-point)", "111100110D0znnnndddd1111NQM0mmmm") // ASIMD +INST(asimd_VPMIN_float, "VPMIN (floating-point)", "111100110D1znnnndddd1111NQM0mmmm") // ASIMD INST(asimd_VRECPS, "VRECPS", "111100100D0znnnndddd1111NQM1mmmm") // ASIMD INST(asimd_VRSQRTS, "VRSQRTS", "111100100D1znnnndddd1111NQM1mmmm") // ASIMD diff --git a/src/frontend/A32/translate/impl/asimd_three_regs.cpp b/src/frontend/A32/translate/impl/asimd_three_regs.cpp index 01873dcc..9b4ba5a2 100644 --- a/src/frontend/A32/translate/impl/asimd_three_regs.cpp +++ b/src/frontend/A32/translate/impl/asimd_three_regs.cpp @@ -803,6 +803,28 @@ bool ArmTranslatorVisitor::asimd_VMIN_float(bool D, bool sz, size_t Vn, size_t V }); } +bool ArmTranslatorVisitor::asimd_VPMAX_float(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) { + if (Q) { + return UndefinedInstruction(); + } + return FloatingPointInstruction(*this, D, sz, Vn, Vd, N, Q, M, Vm, [this](const auto&, const auto& reg_n, const auto& reg_m) { + const auto bottom = ir.VectorDeinterleaveEvenLower(32, reg_n, reg_m); + const auto top = ir.VectorDeinterleaveOddLower(32, reg_n, reg_m); + return ir.FPVectorMax(32, bottom, top, false); + }); +} + +bool ArmTranslatorVisitor::asimd_VPMIN_float(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) { + if (Q) { + return UndefinedInstruction(); + } + return FloatingPointInstruction(*this, D, sz, Vn, Vd, N, Q, M, Vm, [this](const auto&, const auto& reg_n, const auto& reg_m) { + const auto bottom = ir.VectorDeinterleaveEvenLower(32, reg_n, reg_m); + const auto top = ir.VectorDeinterleaveOddLower(32, reg_n, reg_m); + return ir.FPVectorMin(32, bottom, top, false); + }); +} + bool ArmTranslatorVisitor::asimd_VRECPS(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) { return FloatingPointInstruction(*this, D, sz, Vn, Vd, N, Q, M, Vm, [this](const auto&, const auto& reg_n, const auto& reg_m) { return ir.FPVectorRecipStepFused(32, reg_n, reg_m, false); diff --git a/src/frontend/A32/translate/impl/translate_arm.h b/src/frontend/A32/translate/impl/translate_arm.h index 0cf490cf..119da898 100644 --- a/src/frontend/A32/translate/impl/translate_arm.h +++ b/src/frontend/A32/translate/impl/translate_arm.h @@ -500,6 +500,8 @@ struct ArmTranslatorVisitor final { bool asimd_VACGE(bool D, bool op, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm); bool asimd_VMAX_float(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm); bool asimd_VMIN_float(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm); + bool asimd_VPMAX_float(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm); + bool asimd_VPMIN_float(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm); bool asimd_VRECPS(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm); bool asimd_VRSQRTS(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);