From 7402d38675d2a084593a13a26d2903331a2ddf7d Mon Sep 17 00:00:00 2001
From: MerryMage <MerryMage@users.noreply.github.com>
Date: Thu, 18 Jun 2020 17:39:56 +0100
Subject: [PATCH] test_arm_instructions: Add vclt.f32 (zero) test

---
 tests/A32/test_arm_instructions.cpp | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/tests/A32/test_arm_instructions.cpp b/tests/A32/test_arm_instructions.cpp
index 11b263f9..1aeb31bb 100644
--- a/tests/A32/test_arm_instructions.cpp
+++ b/tests/A32/test_arm_instructions.cpp
@@ -465,3 +465,23 @@ TEST_CASE("arm: PackedAbsDiffSumS8", "[arm][A32]") {
     REQUIRE(jit.Regs()[15] == 0x00000008);
     REQUIRE(jit.Cpsr() == 0xb0000010);
 }
+
+TEST_CASE("arm: vclt.f32 with zero", "[arm][A32][.]") {
+    ArmTestEnv test_env;
+    A32::Jit jit{GetUserConfig(&test_env)};
+    test_env.code_mem = {
+        0xf3b93628, // vclt.f32 d3, d24, #0
+        0xeafffffe, // b +#0
+    };
+
+    jit.ExtRegs()[48] = 0x3a87d9f1;
+    jit.ExtRegs()[49] = 0x80796dc0;
+
+    jit.SetCpsr(0x000001d0); // User-mode
+
+    test_env.ticks_left = 2;
+    jit.Run();
+
+    REQUIRE(jit.ExtRegs()[6] == 0x00000000);
+    REQUIRE(jit.ExtRegs()[7] == 0x00000000);
+}