From 7840caef6e8d8468a605450d5ca72e35078c8f01 Mon Sep 17 00:00:00 2001 From: Merry Date: Sun, 24 Jul 2022 18:56:50 +0100 Subject: [PATCH] emit_arm64_data_processing: Fix bug in EmitBitOp --- .../backend/arm64/emit_arm64_data_processing.cpp | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/dynarmic/backend/arm64/emit_arm64_data_processing.cpp b/src/dynarmic/backend/arm64/emit_arm64_data_processing.cpp index a4b32e84..1e2eea4e 100644 --- a/src/dynarmic/backend/arm64/emit_arm64_data_processing.cpp +++ b/src/dynarmic/backend/arm64/emit_arm64_data_processing.cpp @@ -768,16 +768,16 @@ static void MaybeBitImm(oaknut::CodeGenerator& code, u64 imm, EmitFn emit_fn) { template static void EmitBitOp(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst, EmitFn1 emit_without_flags, EmitFn2 emit_with_flags = nullptr) { - const auto nz_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetNZFromOp); - const auto nzcv_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetNZCVFromOp); - ASSERT(!(nz_inst && nzcv_inst)); - const auto flag_inst = nz_inst ? nz_inst : nzcv_inst; - auto args = ctx.reg_alloc.GetArgumentInfo(inst); auto Rresult = ctx.reg_alloc.WriteReg(inst); auto Ra = ctx.reg_alloc.ReadReg(args[0]); if constexpr (!std::is_same_v) { + const auto nz_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetNZFromOp); + const auto nzcv_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetNZCVFromOp); + ASSERT(!(nz_inst && nzcv_inst)); + const auto flag_inst = nz_inst ? nz_inst : nzcv_inst; + if (flag_inst) { auto Wflags = ctx.reg_alloc.WriteFlags(flag_inst); @@ -804,7 +804,7 @@ static void EmitBitOp(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* i auto Rb = ctx.reg_alloc.ReadReg(args[1]); RegAlloc::Realize(Rresult, Ra, Rb); - emit_without_flags(Rresult, Rb, Rb); + emit_without_flags(Rresult, Ra, Rb); } }