diff --git a/src/frontend/arm_types.h b/src/frontend/arm_types.h
index df85b699..54cb73ec 100644
--- a/src/frontend/arm_types.h
+++ b/src/frontend/arm_types.h
@@ -160,17 +160,17 @@ inline size_t RegNumber(ExtReg reg) {
     }
 }
 
-inline Reg operator+(Reg reg, int number) {
+inline Reg operator+(Reg reg, size_t number) {
     ASSERT(reg != Reg::INVALID_REG);
 
-    int new_reg = static_cast<int>(reg) + number;
+    size_t new_reg = static_cast<size_t>(reg) + number;
     ASSERT(new_reg >= 0 && new_reg <= 15);
 
     return static_cast<Reg>(new_reg);
 }
 
-inline ExtReg operator+(ExtReg reg, int number) {
-    ExtReg new_reg = static_cast<ExtReg>(static_cast<int>(reg) + number);
+inline ExtReg operator+(ExtReg reg, size_t number) {
+    ExtReg new_reg = static_cast<ExtReg>(static_cast<size_t>(reg) + number);
 
     ASSERT((reg >= ExtReg::S0 && reg <= ExtReg::S31 && new_reg >= ExtReg::S0 && new_reg <= ExtReg::S31)
            || (reg >= ExtReg::D0 && reg <= ExtReg::D31 && new_reg >= ExtReg::D0 && new_reg <= ExtReg::D31));
diff --git a/src/frontend/translate/translate_arm/vfp2.cpp b/src/frontend/translate/translate_arm/vfp2.cpp
index 1f65943d..061cad80 100644
--- a/src/frontend/translate/translate_arm/vfp2.cpp
+++ b/src/frontend/translate/translate_arm/vfp2.cpp
@@ -362,7 +362,7 @@ bool ArmTranslatorVisitor::vfp2_VSQRT(Cond cond, bool D, size_t Vd, bool sz, boo
 
 bool ArmTranslatorVisitor::vfp2_VPOP(Cond cond, bool D, size_t Vd, bool sz, Imm8 imm8) {
     const ExtReg d = ToExtReg(sz, Vd, D);
-    const unsigned regs = sz ? imm8 >> 1 : imm8;
+    const size_t regs = sz ? imm8 >> 1 : imm8;
 
     if (regs == 0 || RegNumber(d)+regs > 32)
         return UnpredictableInstruction();
@@ -373,7 +373,7 @@ bool ArmTranslatorVisitor::vfp2_VPOP(Cond cond, bool D, size_t Vd, bool sz, Imm8
     if (ConditionPassed(cond)) {
         auto address = ir.GetRegister(Reg::SP);
 
-        for (unsigned i = 0; i < regs; ++i) {
+        for (size_t i = 0; i < regs; ++i) {
             if (sz) {
                 auto lo = ir.ReadMemory32(address);
                 address = ir.Add(address, ir.Imm32(4));
@@ -396,7 +396,7 @@ bool ArmTranslatorVisitor::vfp2_VPOP(Cond cond, bool D, size_t Vd, bool sz, Imm8
 bool ArmTranslatorVisitor::vfp2_VPUSH(Cond cond, bool D, size_t Vd, bool sz, Imm8 imm8) {
     u32 imm32 = imm8 << 2;
     const ExtReg d = ToExtReg(sz, Vd, D);
-    const unsigned regs = sz ? imm8 >> 1 : imm8;
+    const size_t regs = sz ? imm8 >> 1 : imm8;
 
     if (regs == 0 || RegNumber(d)+regs > 32)
         return UnpredictableInstruction();
@@ -408,7 +408,7 @@ bool ArmTranslatorVisitor::vfp2_VPUSH(Cond cond, bool D, size_t Vd, bool sz, Imm
         auto address = ir.Sub(ir.GetRegister(Reg::SP), ir.Imm32(imm32));
         ir.SetRegister(Reg::SP, address);
 
-        for (unsigned i = 0; i < regs; ++i) {
+        for (size_t i = 0; i < regs; ++i) {
             if (sz) {
                 const auto d_u64 = ir.TransferFromFP64(ir.GetExtendedRegister(d + i));
                 auto lo = ir.LeastSignificantWord(d_u64);