diff --git a/src/dynarmic/backend/arm64/a32_address_space.cpp b/src/dynarmic/backend/arm64/a32_address_space.cpp
index f839f3c3..a060b8f5 100644
--- a/src/dynarmic/backend/arm64/a32_address_space.cpp
+++ b/src/dynarmic/backend/arm64/a32_address_space.cpp
@@ -196,6 +196,9 @@ void A32AddressSpace::EmitPrelude() {
         code.STR(Wscratch1, SP, offsetof(StackLayout, save_host_fpcr));
         code.MSR(oaknut::SystemReg::FPCR, Xscratch0);
 
+        code.LDAR(Wscratch0, Xhalt);
+        code.CBNZ(Wscratch0, return_from_run_code);
+
         code.BR(X19);
     }
 
@@ -221,6 +224,7 @@ void A32AddressSpace::EmitPrelude() {
         oaknut::Label step_hr_loop;
         code.l(step_hr_loop);
         code.LDAXR(Wscratch0, Xhalt);
+        code.CBNZ(Wscratch0, return_from_run_code);
         code.ORR(Wscratch0, Wscratch0, static_cast<u32>(HaltReason::Step));
         code.STLXR(Wscratch1, Wscratch0, Xhalt);
         code.CBNZ(Wscratch1, step_hr_loop);
diff --git a/tests/A32/test_arm_instructions.cpp b/tests/A32/test_arm_instructions.cpp
index 5976b6af..e1459264 100644
--- a/tests/A32/test_arm_instructions.cpp
+++ b/tests/A32/test_arm_instructions.cpp
@@ -239,6 +239,7 @@ TEST_CASE("arm: Test InvalidateCacheRange", "[arm][A32]") {
 
     test_env.ticks_left = 4;
     jit.Run();
+    jit.Run();
 
     REQUIRE(jit.Regs()[0] == 5);
     REQUIRE(jit.Regs()[1] == 7);