diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc
index e721d5bf..8013a2a6 100644
--- a/src/frontend/A64/decoder/a64.inc
+++ b/src/frontend/A64/decoder/a64.inc
@@ -458,7 +458,7 @@ INST(ADD_1,                  "ADD (vector)",                              "01011
 //INST(UQSUB_1,                "UQSUB",                                     "01111110zz1mmmmm001011nnnnnddddd")
 INST(CMHI_1,                 "CMHI (register)",                           "01111110zz1mmmmm001101nnnnnddddd")
 INST(CMHS_1,                 "CMHS (register)",                           "01111110zz1mmmmm001111nnnnnddddd")
-//INST(USHL_1,                 "USHL",                                      "01111110zz1mmmmm010001nnnnnddddd")
+INST(USHL_1,                 "USHL",                                      "01111110zz1mmmmm010001nnnnnddddd")
 //INST(UQSHL_reg_1,            "UQSHL (register)",                          "01111110zz1mmmmm010011nnnnnddddd")
 //INST(URSHL_1,                "URSHL",                                     "01111110zz1mmmmm010101nnnnnddddd")
 //INST(UQRSHL_1,               "UQRSHL",                                    "01111110zz1mmmmm010111nnnnnddddd")
diff --git a/src/frontend/A64/translate/impl/simd_scalar_three_same.cpp b/src/frontend/A64/translate/impl/simd_scalar_three_same.cpp
index 05ae4277..7a132c0c 100644
--- a/src/frontend/A64/translate/impl/simd_scalar_three_same.cpp
+++ b/src/frontend/A64/translate/impl/simd_scalar_three_same.cpp
@@ -130,4 +130,17 @@ bool TranslatorVisitor::SUB_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
     return true;
 }
 
+bool TranslatorVisitor::USHL_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
+    if (size != 0b11) {
+        return ReservedValue();
+    }
+
+    const IR::U128 operand1 = V(64, Vn);
+    const IR::U128 operand2 = V(64, Vm);
+    const IR::U128 result = ir.VectorLogicalVShift(64, operand1, operand2);
+
+    V(64, Vd, result);
+    return true;
+}
+
 } // namespace Dynarmic::A64