extension: Implement SXTAB16 and SXTB16
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1 changed files with 25 additions and 4 deletions
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@ -29,8 +29,19 @@ bool ArmTranslatorVisitor::arm_SXTAB(Cond cond, Reg n, Reg d, SignExtendRotation
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}
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bool ArmTranslatorVisitor::arm_SXTAB16(Cond cond, Reg n, Reg d, SignExtendRotation rotate, Reg m) {
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bool ArmTranslatorVisitor::arm_SXTAB16(Cond cond, Reg n, Reg d, SignExtendRotation rotate, Reg m) {
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UNUSED(cond, n, d, rotate, m);
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if (d == Reg::PC || m == Reg::PC)
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return InterpretThisInstruction();
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return UnpredictableInstruction();
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// SXTAB16 <Rd>, <Rn>, <Rm>, <rotate>
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if (ConditionPassed(cond)) {
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auto rotated = Rotate(ir, m, rotate);
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auto low_byte = ir.And(rotated, ir.Imm32(0x00FF00FF));
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auto sign_bit = ir.And(rotated, ir.Imm32(0x00800080));
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auto addend = ir.Or(low_byte, ir.Mul(sign_bit, ir.Imm32(0x1FE)));
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auto result = ir.PackedAddU16(addend, ir.GetRegister(n)).result;
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ir.SetRegister(d, result);
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}
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return true;
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}
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}
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bool ArmTranslatorVisitor::arm_SXTAH(Cond cond, Reg n, Reg d, SignExtendRotation rotate, Reg m) {
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bool ArmTranslatorVisitor::arm_SXTAH(Cond cond, Reg n, Reg d, SignExtendRotation rotate, Reg m) {
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@ -61,8 +72,18 @@ bool ArmTranslatorVisitor::arm_SXTB(Cond cond, Reg d, SignExtendRotation rotate,
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}
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}
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bool ArmTranslatorVisitor::arm_SXTB16(Cond cond, Reg d, SignExtendRotation rotate, Reg m) {
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bool ArmTranslatorVisitor::arm_SXTB16(Cond cond, Reg d, SignExtendRotation rotate, Reg m) {
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UNUSED(cond, d, rotate, m);
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if (d == Reg::PC || m == Reg::PC)
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return InterpretThisInstruction();
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return UnpredictableInstruction();
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// SXTB16 <Rd>, <Rm>, <rotate>
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if (ConditionPassed(cond)) {
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auto rotated = Rotate(ir, m, rotate);
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auto low_byte = ir.And(rotated, ir.Imm32(0x00FF00FF));
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auto sign_bit = ir.And(rotated, ir.Imm32(0x00800080));
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auto result = ir.Or(low_byte, ir.Mul(sign_bit, ir.Imm32(0x1FE)));
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ir.SetRegister(d, result);
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}
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return true;
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}
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}
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bool ArmTranslatorVisitor::arm_SXTH(Cond cond, Reg d, SignExtendRotation rotate, Reg m) {
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bool ArmTranslatorVisitor::arm_SXTH(Cond cond, Reg d, SignExtendRotation rotate, Reg m) {
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