diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc
index ed7d77b3..c2d24228 100644
--- a/src/frontend/A64/decoder/a64.inc
+++ b/src/frontend/A64/decoder/a64.inc
@@ -638,7 +638,7 @@ INST(NEG_2,                  "NEG (vector)",                              "0Q101
 //INST(UCVTF_int_3,            "UCVTF (vector, integer)",                   "0Q10111001111001110110nnnnnddddd")
 //INST(UCVTF_int_4,            "UCVTF (vector, integer)",                   "0Q1011100z100001110110nnnnnddddd")
 INST(NOT,                    "NOT",                                       "0Q10111000100000010110nnnnnddddd")
-//INST(RBIT_asimd,             "RBIT (vector)",                             "0Q10111001100000010110nnnnnddddd")
+INST(RBIT_asimd,             "RBIT (vector)",                             "0Q10111001100000010110nnnnnddddd")
 //INST(FNEG_1,                 "FNEG (vector)",                             "0Q10111011111000111110nnnnnddddd")
 //INST(FNEG_2,                 "FNEG (vector)",                             "0Q1011101z100000111110nnnnnddddd")
 //INST(FRINTI_1,               "FRINTI (vector)",                           "0Q10111011111001100110nnnnnddddd")
diff --git a/src/frontend/A64/translate/impl/simd_two_register_misc.cpp b/src/frontend/A64/translate/impl/simd_two_register_misc.cpp
index 03a65c08..03cc3b40 100644
--- a/src/frontend/A64/translate/impl/simd_two_register_misc.cpp
+++ b/src/frontend/A64/translate/impl/simd_two_register_misc.cpp
@@ -125,4 +125,14 @@ bool TranslatorVisitor::NOT(bool Q, Vec Vn, Vec Vd) {
     return true;
 }
 
+bool TranslatorVisitor::RBIT_asimd(bool Q, Vec Vn, Vec Vd) {
+    const size_t datasize = Q ? 128 : 64;
+
+    const IR::U128 data = V(datasize, Vn);
+    const IR::U128 result = ir.VectorReverseBits(data);
+
+    V(datasize, Vd, result);
+    return true;
+}
+
 } // namespace Dynarmic::A64