A32: Rearrange translators for ASIMD Three Registers

* Separate Three Registers with Different Lengths from Same Lengths decoders

src/CMakeLists.txt

@@ -126,7 +126,7 @@ if ("A32" IN_LIST DYNARMIC_FRONTENDS)
         frontend/A32/translate/impl/asimd_load_store_structures.cpp
         frontend/A32/translate/impl/asimd_misc.cpp
         frontend/A32/translate/impl/asimd_one_reg_modified_immediate.cpp
-        frontend/A32/translate/impl/asimd_three_same.cpp
+        frontend/A32/translate/impl/asimd_three_regs.cpp
         frontend/A32/translate/impl/asimd_two_regs_misc.cpp
         frontend/A32/translate/impl/asimd_two_regs_scalar.cpp
         frontend/A32/translate/impl/asimd_two_regs_shift.cpp

src/frontend/A32/decoder/asimd.inc

@@ -20,17 +20,13 @@ INST(asimd_VRSHL,           "VRSHL",                    "1111001U0Dzznnnndddd010
 //INST(asimd_VQRSHL,          "VQRSHL",                   "1111001U0-CC--------0101---1----") // ASIMD
 INST(asimd_VMAX,            "VMAX/VMIN",                "1111001U0Dzznnnnmmmm0110NQMommmm") // ASIMD
 INST(asimd_VABD,            "VABD",                     "1111001U0Dzznnnndddd0111NQM0mmmm") // ASIMD
-INST(asimd_VABDL,           "VABDL",                    "1111001U1Dzznnnndddd0111N0M0mmmm") // ASIMD
 INST(asimd_VABA,            "VABA",                     "1111001U0Dzznnnndddd0111NQM1mmmm") // ASIMD
-INST(asimd_VABAL,           "VABAL",                    "1111001U1Dzznnnndddd0101N0M0mmmm") // ASIMD
 INST(asimd_VADD_int,        "VADD (integer)",           "111100100Dzznnnndddd1000NQM0mmmm") // ASIMD
 INST(asimd_VSUB_int,        "VSUB (integer)",           "111100110Dzznnnndddd1000NQM0mmmm") // ASIMD
 INST(asimd_VTST,            "VTST",                     "111100100Dzznnnndddd1000NQM1mmmm") // ASIMD
 INST(asimd_VCEQ_reg,        "VCEG (register)",          "111100110Dzznnnndddd1000NQM1mmmm") // ASIMD
 INST(asimd_VMLA,            "VMLA/VMLS",                "1111001o0Dzznnnndddd1001NQM0mmmm") // ASIMD
-INST(asimd_VMLAL,           "VMLAL/VMLSL",              "1111001U1Dzznnnndddd10o0N0M0mmmm") // ASIMD
 INST(asimd_VMUL,            "VMUL",                     "1111001P0Dzznnnndddd1001NQM1mmmm") // ASIMD
-INST(asimd_VMULL,           "VMULL",                    "1111001U1Dzznnnndddd11P0N0M0mmmm") // ASIMD
 //INST(asimd_VPMAX,           "VPMAX/VPMIN",              "1111001U0-CC--------1010---B----") // ASIMD
 INST(asimd_VQDMULH,         "VQDMULH",                  "111100100Dzznnnndddd1011NQM0mmmm") // ASIMD
 INST(asimd_VQRDMULH,        "VQRDMULH",                 "111100110Dzznnnndddd1011NQM0mmmm") // ASIMD
@@ -59,13 +55,13 @@ INST(asimd_VRSQRTS,         "VRSQRTS",                  "111100100D1znnnndddd111
 //INST(asimd_VSUBL,           "VSUBL/VSUBW",              "1111001-1-----------001--0-0----") // ASIMD
 //INST(asimd_VADDHN,          "VADDHN",                   "111100101-----------0100-0-0----") // ASIMD
 //INST(asimd_VRADDHN,         "VRADDHN",                  "111100111-----------0100-0-0----") // ASIMD
-// VABAL
+INST(asimd_VABAL,           "VABAL",                    "1111001U1Dzznnnndddd0101N0M0mmmm") // ASIMD
 //INST(asimd_VSUBHN,          "VSUBHN",                   "111100101-----------0110-0-0----") // ASIMD
 //INST(asimd_VRSUBHN,         "VRSUBHN",                  "111100111-----------0110-0-0----") // ASIMD
-// VABDL
+INST(asimd_VABDL,           "VABDL",                    "1111001U1Dzznnnndddd0111N0M0mmmm") // ASIMD
-// VMLAL
+INST(asimd_VMLAL,           "VMLAL/VMLSL",              "1111001U1Dzznnnndddd10o0N0M0mmmm") // ASIMD
 //INST(asimd_VQDMLAL,         "VQDMLAL",                  "111100101-----------10-1-0-0----") // ASIMD
-// VMULL
+INST(asimd_VMULL,           "VMULL",                    "1111001U1Dzznnnndddd11P0N0M0mmmm") // ASIMD
 //INST(asimd_VQDMULL,         "VQDMULL",                  "111100101-----------1101-0-0----") // ASIMD
 
 // Two registers and a scalar

src/frontend/A32/translate/impl/asimd_three_regs.cpp

@@ -213,6 +213,8 @@ bool AbsoluteDifferenceLong(ArmTranslatorVisitor& v, bool U, bool D, size_t sz,
 }
 } // Anonymous namespace
 
+// ASIMD Three registers of the same length
+
 bool ArmTranslatorVisitor::asimd_VHADD(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) {
     if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) {
         return UndefinedInstruction();
@@ -383,18 +385,10 @@ bool ArmTranslatorVisitor::asimd_VABD(bool U, bool D, size_t sz, size_t Vn, size
     return AbsoluteDifference(*this, U, D, sz, Vn, Vd, N, Q, M, Vm, AccumulateBehavior::None);
 }
 
-bool ArmTranslatorVisitor::asimd_VABDL(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool M, size_t Vm) {
-    return AbsoluteDifferenceLong(*this, U, D, sz, Vn, Vd, N, M, Vm, AccumulateBehavior::None);
-}
-
 bool ArmTranslatorVisitor::asimd_VABA(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) {
     return AbsoluteDifference(*this, U, D, sz, Vn, Vd, N, Q, M, Vm, AccumulateBehavior::Accumulate);
 }
 
-bool ArmTranslatorVisitor::asimd_VABAL(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool M, size_t Vm) {
-    return AbsoluteDifferenceLong(*this, U, D, sz, Vn, Vd, N, M, Vm, AccumulateBehavior::Accumulate);
-}
-
 bool ArmTranslatorVisitor::asimd_VADD_int(bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) {
     if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) {
         return UndefinedInstruction();
@@ -570,36 +564,6 @@ bool ArmTranslatorVisitor::asimd_VMLA(bool op, bool D, size_t sz, size_t Vn, siz
     return true;
 }
 
-bool ArmTranslatorVisitor::asimd_VMLAL(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool op, bool N, bool M, size_t Vm) {
-    if (sz == 0b11) {
-        return UndefinedInstruction();
-    }
-
-    if (Common::Bit<0>(Vd)) {
-        return UndefinedInstruction();
-    }
-
-    const size_t esize = 8U << sz;
-    const auto d = ToVector(true, Vd, D);
-    const auto m = ToVector(false, Vm, M);
-    const auto n = ToVector(false, Vn, N);
-
-    const auto extend_reg = [&](const auto& reg) {
-        return U ? ir.VectorZeroExtend(esize, reg)
-                 : ir.VectorSignExtend(esize, reg);
-    };
-
-    const auto reg_d = ir.GetVector(d);
-    const auto reg_n = ir.GetVector(n);
-    const auto reg_m = ir.GetVector(m);
-    const auto multiply = ir.VectorMultiply(2 * esize, extend_reg(reg_n), extend_reg(reg_m));
-    const auto result = op ? ir.VectorSub(2 * esize, reg_d, multiply)
-                           : ir.VectorAdd(2 * esize, reg_d, multiply);
-
-    ir.SetVector(d, result);
-    return true;
-}
-
 bool ArmTranslatorVisitor::asimd_VMUL(bool P, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) {
     if (sz == 0b11 || (P && sz != 0b00)) {
         return UndefinedInstruction();
@@ -668,29 +632,6 @@ bool ArmTranslatorVisitor::asimd_VQRDMULH(bool D, size_t sz, size_t Vn, size_t V
     return true;
 }
 
-bool ArmTranslatorVisitor::asimd_VMULL(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool P, bool N, bool M, size_t Vm) {
-    if (sz == 0b11 || (P & (U || sz == 0b10)) || Common::Bit<0>(Vd)) {
-        return UndefinedInstruction();
-    }
-
-    const size_t esize = P ? (sz == 0b00 ? 8 : 64) : 8U << sz;
-    const auto d = ToVector(true, Vd, D);
-    const auto m = ToVector(false, Vm, M);
-    const auto n = ToVector(false, Vn, N);
-
-    const auto extend_reg = [&](const auto& reg) {
-        return U ? ir.VectorZeroExtend(esize, reg) : ir.VectorSignExtend(esize, reg);
-    };
-
-    const auto reg_n = ir.GetVector(n);
-    const auto reg_m = ir.GetVector(m);
-    const auto result = P ? ir.VectorPolynomialMultiplyLong(esize, reg_m, reg_n)
-                          : ir.VectorMultiply(2 * esize, extend_reg(reg_m), extend_reg(reg_n));
-
-    ir.SetVector(d, result);
-    return true;
-}
-
 bool ArmTranslatorVisitor::asimd_VPADD(bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) {
     if (Q || sz == 0b11) {
         return UndefinedInstruction();
@@ -807,4 +748,67 @@ bool ArmTranslatorVisitor::asimd_VRSQRTS(bool D, bool sz, size_t Vn, size_t Vd,
     });
 }
 
+// ASIMD Three registers of different length
+
+bool ArmTranslatorVisitor::asimd_VABAL(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool M, size_t Vm) {
+    return AbsoluteDifferenceLong(*this, U, D, sz, Vn, Vd, N, M, Vm, AccumulateBehavior::Accumulate);
+}
+
+bool ArmTranslatorVisitor::asimd_VABDL(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool M, size_t Vm) {
+    return AbsoluteDifferenceLong(*this, U, D, sz, Vn, Vd, N, M, Vm, AccumulateBehavior::None);
+}
+
+bool ArmTranslatorVisitor::asimd_VMLAL(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool op, bool N, bool M, size_t Vm) {
+    if (sz == 0b11) {
+        return UndefinedInstruction();
+    }
+
+    if (Common::Bit<0>(Vd)) {
+        return UndefinedInstruction();
+    }
+
+    const size_t esize = 8U << sz;
+    const auto d = ToVector(true, Vd, D);
+    const auto m = ToVector(false, Vm, M);
+    const auto n = ToVector(false, Vn, N);
+
+    const auto extend_reg = [&](const auto& reg) {
+        return U ? ir.VectorZeroExtend(esize, reg)
+                 : ir.VectorSignExtend(esize, reg);
+    };
+
+    const auto reg_d = ir.GetVector(d);
+    const auto reg_n = ir.GetVector(n);
+    const auto reg_m = ir.GetVector(m);
+    const auto multiply = ir.VectorMultiply(2 * esize, extend_reg(reg_n), extend_reg(reg_m));
+    const auto result = op ? ir.VectorSub(2 * esize, reg_d, multiply)
+                           : ir.VectorAdd(2 * esize, reg_d, multiply);
+
+    ir.SetVector(d, result);
+    return true;
+}
+
+bool ArmTranslatorVisitor::asimd_VMULL(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool P, bool N, bool M, size_t Vm) {
+    if (sz == 0b11 || (P & (U || sz == 0b10)) || Common::Bit<0>(Vd)) {
+        return UndefinedInstruction();
+    }
+
+    const size_t esize = P ? (sz == 0b00 ? 8 : 64) : 8U << sz;
+    const auto d = ToVector(true, Vd, D);
+    const auto m = ToVector(false, Vm, M);
+    const auto n = ToVector(false, Vn, N);
+
+    const auto extend_reg = [&](const auto& reg) {
+        return U ? ir.VectorZeroExtend(esize, reg) : ir.VectorSignExtend(esize, reg);
+    };
+
+    const auto reg_n = ir.GetVector(n);
+    const auto reg_m = ir.GetVector(m);
+    const auto result = P ? ir.VectorPolynomialMultiplyLong(esize, reg_m, reg_n)
+                          : ir.VectorMultiply(2 * esize, extend_reg(reg_m), extend_reg(reg_n));
+
+    ir.SetVector(d, result);
+    return true;
+}
+
 } // namespace Dynarmic::A32