From 86b7626a2f9837d4e80cb07fb960ad1a231b2772 Mon Sep 17 00:00:00 2001 From: Lioncash Date: Sat, 13 Apr 2019 19:05:23 -0400 Subject: [PATCH] A64: Implement half-precision vector variant of FRECPS --- src/frontend/A64/decoder/a64.inc | 2 +- src/frontend/A64/translate/impl/simd_three_same.cpp | 12 ++++++++++++ 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc index 3fd8eff2..4558518f 100644 --- a/src/frontend/A64/decoder/a64.inc +++ b/src/frontend/A64/decoder/a64.inc @@ -575,7 +575,7 @@ INST(INS_elt, "INS (element)", "01101 // Data Processing - FP and SIMD - SIMD Three same //INST(FMULX_vec_3, "FMULX", "0Q001110010mmmmm000111nnnnnddddd") //INST(FCMEQ_reg_3, "FCMEQ (register)", "0Q001110010mmmmm001001nnnnnddddd") -//INST(FRECPS_3, "FRECPS", "0Q001110010mmmmm001111nnnnnddddd") +INST(FRECPS_3, "FRECPS", "0Q001110010mmmmm001111nnnnnddddd") //INST(FRSQRTS_3, "FRSQRTS", "0Q001110110mmmmm001111nnnnnddddd") //INST(FCMGE_reg_3, "FCMGE (register)", "0Q101110010mmmmm001001nnnnnddddd") //INST(FACGE_3, "FACGE", "0Q101110010mmmmm001011nnnnnddddd") diff --git a/src/frontend/A64/translate/impl/simd_three_same.cpp b/src/frontend/A64/translate/impl/simd_three_same.cpp index a484dc17..da8939d5 100644 --- a/src/frontend/A64/translate/impl/simd_three_same.cpp +++ b/src/frontend/A64/translate/impl/simd_three_same.cpp @@ -939,6 +939,18 @@ bool TranslatorVisitor::FSUB_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) { return true; } +bool TranslatorVisitor::FRECPS_3(bool Q, Vec Vm, Vec Vn, Vec Vd) { + const size_t esize = 16; + const size_t datasize = Q ? 128 : 64; + + const IR::U128 operand1 = V(datasize, Vn); + const IR::U128 operand2 = V(datasize, Vm); + const IR::U128 result = ir.FPVectorRecipStepFused(esize, operand1, operand2); + + V(datasize, Vd, result); + return true; +} + bool TranslatorVisitor::FRECPS_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) { if (sz && !Q) { return ReservedValue();