diff --git a/src/frontend/A32/decoder/arm.inc b/src/frontend/A32/decoder/arm.inc
index ee9f7de1..d8ba8d32 100644
--- a/src/frontend/A32/decoder/arm.inc
+++ b/src/frontend/A32/decoder/arm.inc
@@ -168,6 +168,7 @@ INST(arm_BFC,           "BFC",                 "cccc0111110vvvvvddddvvvvv0011111
 INST(arm_BFI,           "BFI",                 "cccc0111110vvvvvddddvvvvv001nnnn") // v6T2
 INST(arm_CLZ,           "CLZ",                 "cccc000101101111dddd11110001mmmm") // v5
 INST(arm_NOP,           "NOP",                 "----0011001000001111000000000000") // v6K
+INST(arm_SBFX,          "SBFX",                "cccc0111101wwwwwddddvvvvv101nnnn") // v6T2
 INST(arm_SEL,           "SEL",                 "cccc01101000nnnndddd11111011mmmm") // v6
 INST(arm_UBFX,          "UBFX",                "cccc0111111wwwwwddddvvvvv101nnnn") // v6T2
 
diff --git a/src/frontend/A32/disassembler/disassembler_arm.cpp b/src/frontend/A32/disassembler/disassembler_arm.cpp
index a6c906fc..be0bbe21 100644
--- a/src/frontend/A32/disassembler/disassembler_arm.cpp
+++ b/src/frontend/A32/disassembler/disassembler_arm.cpp
@@ -598,6 +598,9 @@ public:
     std::string arm_RBIT(Cond cond, Reg d, Reg m) {
         return fmt::format("rbit{} {}, {}", CondToString(cond), d, m);
     }
+    std::string arm_SBFX(Cond cond, Imm5 widthm1, Reg d, Imm5 lsb, Reg n) {
+        return fmt::format("sbfx{} {}, {}, #{}, #{}", CondToString(cond), d, n, lsb, widthm1 + 1);
+    }
     std::string arm_SEL(Cond cond, Reg n, Reg d, Reg m) {
         return fmt::format("sel{} {}, {}, {}", CondToString(cond), d, n, m);
     }
diff --git a/src/frontend/A32/translate/translate_arm/misc.cpp b/src/frontend/A32/translate/translate_arm/misc.cpp
index 9670875d..88026633 100644
--- a/src/frontend/A32/translate/translate_arm/misc.cpp
+++ b/src/frontend/A32/translate/translate_arm/misc.cpp
@@ -67,6 +67,33 @@ bool ArmTranslatorVisitor::arm_CLZ(Cond cond, Reg d, Reg m) {
     return true;
 }
 
+// SBFX<c> <Rd>, <Rn>, #<lsb>, #<width>
+bool ArmTranslatorVisitor::arm_SBFX(Cond cond, Imm5 widthm1, Reg d, Imm5 lsb, Reg n) {
+    if (d == Reg::PC || n == Reg::PC) {
+        return UnpredictableInstruction();
+    }
+
+    const u32 msb = u32{lsb} + widthm1;
+    if (msb >= Common::BitSize<u32>()) {
+        return UnpredictableInstruction();
+    }
+
+    if (!ConditionPassed(cond)) {
+        return true;
+    }
+
+    constexpr size_t max_width = Common::BitSize<u32>();
+    const u8 width = widthm1 + 1;
+    const u8 left_shift_amount = static_cast<u8>(max_width - width - lsb);
+    const u8 right_shift_amount = static_cast<u8>(max_width - width);
+    const IR::U32 operand = ir.GetRegister(n);
+    const IR::U32 tmp = ir.LogicalShiftLeft(operand, ir.Imm8(left_shift_amount));
+    const IR::U32 result = ir.ArithmeticShiftRight(tmp, ir.Imm8(right_shift_amount));
+
+    ir.SetRegister(d, result);
+    return true;
+}
+
 // SEL<c> <Rd>, <Rn>, <Rm>
 bool ArmTranslatorVisitor::arm_SEL(Cond cond, Reg n, Reg d, Reg m) {
     if (n == Reg::PC || d == Reg::PC || m == Reg::PC) {
diff --git a/src/frontend/A32/translate/translate_arm/translate_arm.h b/src/frontend/A32/translate/translate_arm/translate_arm.h
index b1cfac68..ff8db053 100644
--- a/src/frontend/A32/translate/translate_arm/translate_arm.h
+++ b/src/frontend/A32/translate/translate_arm/translate_arm.h
@@ -212,6 +212,7 @@ struct ArmTranslatorVisitor final {
     bool arm_CLZ(Cond cond, Reg d, Reg m);
     bool arm_NOP() { return true; }
     bool arm_RBIT(Cond cond, Reg d, Reg m);
+    bool arm_SBFX(Cond cond, Imm5 widthm1, Reg d, Imm5 lsb, Reg n);
     bool arm_SEL(Cond cond, Reg n, Reg d, Reg m);
     bool arm_UBFX(Cond cond, Imm5 widthm1, Reg d, Imm5 lsb, Reg n);
 
diff --git a/tests/A32/fuzz_arm.cpp b/tests/A32/fuzz_arm.cpp
index 87029a9f..58d0df20 100644
--- a/tests/A32/fuzz_arm.cpp
+++ b/tests/A32/fuzz_arm.cpp
@@ -1093,7 +1093,7 @@ TEST_CASE("Test ARM misc instructions", "[JitX64][A32]") {
         // R15 as Rd, or Rm is UNPREDICTABLE
         return Bits<0, 3>(instr) != 0b1111 && Bits<12, 15>(instr) != 0b1111;
     };
-    const auto is_ubfx_valid = [](u32 instr) {
+    const auto is_extract_valid = [](u32 instr) {
         const u32 lsb = Bits<7, 11>(instr);
         const u32 widthm1 = Bits<16, 20>(instr);
         const u32 msb = lsb + widthm1;
@@ -1108,7 +1108,8 @@ TEST_CASE("Test ARM misc instructions", "[JitX64][A32]") {
         InstructionGenerator("cccc0111110vvvvvddddvvvvv0011111", is_bfc_bfi_valid), // BFC
         InstructionGenerator("cccc0111110vvvvvddddvvvvv001nnnn", is_bfc_bfi_valid), // BFI
         InstructionGenerator("cccc000101101111dddd11110001mmmm", is_clz_valid),     // CLZ
-        InstructionGenerator("cccc0111111wwwwwddddvvvvv101nnnn", is_ubfx_valid),    // UBFX
+        InstructionGenerator("cccc0111101wwwwwddddvvvvv101nnnn", is_extract_valid), // SBFX
+        InstructionGenerator("cccc0111111wwwwwddddvvvvv101nnnn", is_extract_valid), // UBFX
     };
 
     FuzzJitArm(1, 1, 10000, [&instructions]() -> u32 {