From 879f21168621d082dc31d26bb83f4ad629dcc259 Mon Sep 17 00:00:00 2001
From: merry <git@mary.rs>
Date: Sat, 26 Mar 2022 14:29:22 +0000
Subject: [PATCH] ir/value: Add AccType to Value

---
 src/dynarmic/CMakeLists.txt            |  1 +
 src/dynarmic/backend/x64/reg_alloc.cpp |  1 +
 src/dynarmic/ir/acc_type.h             | 28 ++++++++++++++++++++++++++
 src/dynarmic/ir/ir_emitter.h           | 19 +----------------
 src/dynarmic/ir/opcodes.cpp            |  1 +
 src/dynarmic/ir/type.h                 |  1 +
 src/dynarmic/ir/value.cpp              | 12 +++++++++++
 src/dynarmic/ir/value.h                |  4 ++++
 8 files changed, 49 insertions(+), 18 deletions(-)
 create mode 100644 src/dynarmic/ir/acc_type.h

diff --git a/src/dynarmic/CMakeLists.txt b/src/dynarmic/CMakeLists.txt
index f40a60f9..c6423337 100644
--- a/src/dynarmic/CMakeLists.txt
+++ b/src/dynarmic/CMakeLists.txt
@@ -75,6 +75,7 @@ add_library(dynarmic
     frontend/imm.h
     interface/exclusive_monitor.h
     interface/optimization_flags.h
+    ir/acc_type.h
     ir/basic_block.cpp
     ir/basic_block.h
     ir/cond.h
diff --git a/src/dynarmic/backend/x64/reg_alloc.cpp b/src/dynarmic/backend/x64/reg_alloc.cpp
index 487194e2..ae53a620 100644
--- a/src/dynarmic/backend/x64/reg_alloc.cpp
+++ b/src/dynarmic/backend/x64/reg_alloc.cpp
@@ -42,6 +42,7 @@ static size_t GetBitWidth(IR::Type type) {
     case IR::Type::Cond:
     case IR::Type::Void:
     case IR::Type::Table:
+    case IR::Type::AccType:
         ASSERT_FALSE("Type {} cannot be represented at runtime", type);
     case IR::Type::Opaque:
         ASSERT_FALSE("Not a concrete type");
diff --git a/src/dynarmic/ir/acc_type.h b/src/dynarmic/ir/acc_type.h
new file mode 100644
index 00000000..1452596a
--- /dev/null
+++ b/src/dynarmic/ir/acc_type.h
@@ -0,0 +1,28 @@
+/* This file is part of the dynarmic project.
+ * Copyright (c) 2022 MerryMage
+ * SPDX-License-Identifier: 0BSD
+ */
+
+#pragma once
+
+namespace Dynarmic::IR {
+
+enum class AccType {
+    NORMAL,
+    VEC,
+    STREAM,
+    VECSTREAM,
+    ATOMIC,
+    ORDERED,
+    ORDEREDRW,
+    LIMITEDORDERED,
+    UNPRIV,
+    IFETCH,
+    PTW,
+    DC,
+    IC,
+    DCZVA,
+    AT,
+};
+
+}  // namespace Dynarmic::IR
diff --git a/src/dynarmic/ir/ir_emitter.h b/src/dynarmic/ir/ir_emitter.h
index 62fa6323..fb8d957c 100644
--- a/src/dynarmic/ir/ir_emitter.h
+++ b/src/dynarmic/ir/ir_emitter.h
@@ -6,6 +6,7 @@
 #pragma once
 
 #include "dynarmic/common/common_types.h"
+#include "dynarmic/ir/acc_type.h"
 #include "dynarmic/ir/basic_block.h"
 #include "dynarmic/ir/location_descriptor.h"
 #include "dynarmic/ir/terminal.h"
@@ -56,24 +57,6 @@ struct UpperAndLower {
     U128 lower;
 };
 
-enum class AccType {
-    NORMAL,
-    VEC,
-    STREAM,
-    VECSTREAM,
-    ATOMIC,
-    ORDERED,
-    ORDEREDRW,
-    LIMITEDORDERED,
-    UNPRIV,
-    IFETCH,
-    PTW,
-    DC,
-    IC,
-    DCZVA,
-    AT,
-};
-
 enum class MemOp {
     LOAD,
     STORE,
diff --git a/src/dynarmic/ir/opcodes.cpp b/src/dynarmic/ir/opcodes.cpp
index 354b8c59..2741e5fb 100644
--- a/src/dynarmic/ir/opcodes.cpp
+++ b/src/dynarmic/ir/opcodes.cpp
@@ -43,6 +43,7 @@ constexpr Type CoprocInfo = Type::CoprocInfo;
 constexpr Type NZCV = Type::NZCVFlags;
 constexpr Type Cond = Type::Cond;
 constexpr Type Table = Type::Table;
+constexpr Type AccType = Type::AccType;
 
 static const std::array opcode_info{
 #define OPCODE(name, type, ...) Meta{#name, type, {__VA_ARGS__}},
diff --git a/src/dynarmic/ir/type.h b/src/dynarmic/ir/type.h
index 0c9eda9f..35c02970 100644
--- a/src/dynarmic/ir/type.h
+++ b/src/dynarmic/ir/type.h
@@ -32,6 +32,7 @@ enum class Type {
     NZCVFlags = 1 << 12,
     Cond = 1 << 13,
     Table = 1 << 14,
+    AccType = 1 << 15,
 };
 
 constexpr Type operator|(Type a, Type b) {
diff --git a/src/dynarmic/ir/value.cpp b/src/dynarmic/ir/value.cpp
index 2132b5be..8cdefa39 100644
--- a/src/dynarmic/ir/value.cpp
+++ b/src/dynarmic/ir/value.cpp
@@ -73,6 +73,11 @@ Value::Value(Cond value)
     inner.imm_cond = value;
 }
 
+Value::Value(AccType value)
+        : type(Type::AccType) {
+    inner.imm_acctype = value;
+}
+
 bool Value::IsIdentity() const {
     if (type == Type::Opaque)
         return inner.inst->GetOpcode() == Opcode::Identity;
@@ -178,6 +183,13 @@ Cond Value::GetCond() const {
     return inner.imm_cond;
 }
 
+AccType Value::GetAccType() const {
+    if (IsIdentity())
+        return inner.inst->GetArg(0).GetAccType();
+    ASSERT(type == Type::AccType);
+    return inner.imm_acctype;
+}
+
 s64 Value::GetImmediateAsS64() const {
     ASSERT(IsImmediate());
 
diff --git a/src/dynarmic/ir/value.h b/src/dynarmic/ir/value.h
index e907614d..9e0b19c7 100644
--- a/src/dynarmic/ir/value.h
+++ b/src/dynarmic/ir/value.h
@@ -25,6 +25,7 @@ enum class Vec;
 namespace Dynarmic::IR {
 
 class Inst;
+enum class AccType;
 enum class Cond;
 
 /**
@@ -49,6 +50,7 @@ public:
     explicit Value(u64 value);
     explicit Value(CoprocessorInfo value);
     explicit Value(Cond value);
+    explicit Value(AccType value);
 
     bool IsIdentity() const;
     bool IsEmpty() const;
@@ -68,6 +70,7 @@ public:
     u64 GetU64() const;
     CoprocessorInfo GetCoprocInfo() const;
     Cond GetCond() const;
+    AccType GetAccType() const;
 
     /**
      * Retrieves the immediate of a Value instance as a signed 64-bit value.
@@ -140,6 +143,7 @@ private:
         u64 imm_u64;
         CoprocessorInfo imm_coproc;
         Cond imm_cond;
+        AccType imm_acctype;
     } inner;
 };
 static_assert(sizeof(Value) <= 2 * sizeof(u64), "IR::Value should be kept small in size");