From 8b98c91ecc398c1ff3920602a47df3cd4d786373 Mon Sep 17 00:00:00 2001
From: Lioncash <mathew1800@gmail.com>
Date: Thu, 18 Jun 2020 11:12:17 -0400
Subject: [PATCH] A32: Implement ASIMD VSHL

---
 src/frontend/A32/decoder/asimd.inc            |  2 +-
 .../translate/impl/asimd_two_regs_shift.cpp   | 47 +++++++++++++++----
 .../A32/translate/impl/translate_arm.h        |  1 +
 3 files changed, 41 insertions(+), 9 deletions(-)

diff --git a/src/frontend/A32/decoder/asimd.inc b/src/frontend/A32/decoder/asimd.inc
index 09b4909b..8388b4e2 100644
--- a/src/frontend/A32/decoder/asimd.inc
+++ b/src/frontend/A32/decoder/asimd.inc
@@ -63,7 +63,7 @@ INST(asimd_SRA,             "SRA",                      "1111001U1Diiiiiidddd000
 INST(asimd_VRSHR,           "VRSHR",                    "1111001U1Diiiiiidddd0010LQM1mmmm") // ASIMD
 INST(asimd_VRSRA,           "VRSRA",                    "1111001U1Diiiiiidddd0011LQM1mmmm") // ASIMD
 //INST(asimd_VSRI,            "VSRI",                     "111100111-vvv-------0100LB-1----") // ASIMD
-//INST(asimd_VSHL,            "VSHL",                     "111100101-vvv-------0101LB-1----") // ASIMD
+INST(asimd_VSHL,            "VSHL",                     "111100101Diiiiiidddd0101LQM1mmmm") // ASIMD
 //INST(asimd_VSLI,            "VSLI",                     "111100111-vvv-------0101LB-1----") // ASIMD
 //INST(asimd_VQSHL,           "VQSHL" ,                   "1111001U1-vvv-------011xLB-1----") // ASIMD
 //INST(asimd_VSHRN,           "VSHRN",                    "111100101-vvv-------100000-1----") // ASIMD
diff --git a/src/frontend/A32/translate/impl/asimd_two_regs_shift.cpp b/src/frontend/A32/translate/impl/asimd_two_regs_shift.cpp
index 2e4c6f5f..65cbaf47 100644
--- a/src/frontend/A32/translate/impl/asimd_two_regs_shift.cpp
+++ b/src/frontend/A32/translate/impl/asimd_two_regs_shift.cpp
@@ -25,14 +25,24 @@ IR::U128 PerformRoundingCorrection(ArmTranslatorVisitor& v, size_t esize, u64 ro
     return v.ir.VectorSub(esize, shifted, round_correction);
 }
 
-std::pair<size_t, size_t> ElementSizeAndShiftAmount(bool L, size_t imm6) {
-    if (L) {
-        return {64, 64 - imm6};
-    }
+std::pair<size_t, size_t> ElementSizeAndShiftAmount(bool right_shift, bool L, size_t imm6) {
+    if (right_shift) {
+        if (L) {
+            return {64, 64 - imm6};
+        }
 
-    const size_t esize = 8U << Common::HighestSetBit(imm6 >> 3);
-    const size_t shift_amount = (esize * 2) - imm6;
-    return {esize, shift_amount};
+        const size_t esize = 8U << Common::HighestSetBit(imm6 >> 3);
+        const size_t shift_amount = (esize * 2) - imm6;
+        return {esize, shift_amount};
+    } else {
+        if (L) {
+            return {64, imm6};
+        }
+
+        const size_t esize = 8U << Common::HighestSetBit(imm6 >> 3);
+        const size_t shift_amount = imm6 - esize;
+        return {esize, shift_amount};
+    }
 }
 
 bool ShiftRight(ArmTranslatorVisitor& v, bool U, bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm,
@@ -46,7 +56,7 @@ bool ShiftRight(ArmTranslatorVisitor& v, bool U, bool D, size_t imm6, size_t Vd,
         return v.UndefinedInstruction();
     }
 
-    const auto [esize, shift_amount] = ElementSizeAndShiftAmount(L, imm6);
+    const auto [esize, shift_amount] = ElementSizeAndShiftAmount(true, L, imm6);
     const auto d = ToVector(Q, Vd, D);
     const auto m = ToVector(Q, Vm, M);
 
@@ -89,4 +99,25 @@ bool ArmTranslatorVisitor::asimd_VRSRA(bool U, bool D, size_t imm6, size_t Vd, b
                       Accumulating::Accumulate, Rounding::Round);
 }
 
+bool ArmTranslatorVisitor::asimd_VSHL(bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm) {
+    if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) {
+        return UndefinedInstruction();
+    }
+
+    // Technically just a related encoding (One register and modified immediate instructions)
+    if (!L && Common::Bits<3, 5>(imm6) == 0) {
+        return UndefinedInstruction();
+    }
+
+    const auto [esize, shift_amount] = ElementSizeAndShiftAmount(false, L, imm6);
+    const auto d = ToVector(Q, Vd, D);
+    const auto m = ToVector(Q, Vm, M);
+
+    const auto reg_m = ir.GetVector(m);
+    const auto result = ir.VectorLogicalShiftLeft(esize, reg_m, static_cast<u8>(shift_amount));
+
+    ir.SetVector(d, result);
+    return true;
+}
+
 } // namespace Dynarmic::A32
diff --git a/src/frontend/A32/translate/impl/translate_arm.h b/src/frontend/A32/translate/impl/translate_arm.h
index b4985135..aeb91380 100644
--- a/src/frontend/A32/translate/impl/translate_arm.h
+++ b/src/frontend/A32/translate/impl/translate_arm.h
@@ -456,6 +456,7 @@ struct ArmTranslatorVisitor final {
     bool asimd_SRA(bool U, bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm);
     bool asimd_VRSHR(bool U, bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm);
     bool asimd_VRSRA(bool U, bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm);
+    bool asimd_VSHL(bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm);
 
     // Advanced SIMD two register, miscellaneous
     bool asimd_VREV(bool D, size_t sz, size_t Vd, size_t op, bool Q, bool M, size_t Vm);