From 8c7a81a3083b64864b5ab6141f6c3719303a519b Mon Sep 17 00:00:00 2001
From: MerryMage <MerryMage@users.noreply.github.com>
Date: Tue, 23 Aug 2016 14:26:50 +0100
Subject: [PATCH] VPOP and VPUSH are floating-point load-store instructions

---
 src/frontend/decoder/vfp2.h                          | 4 ++--
 src/frontend/disassembler/disassembler_arm.cpp       | 6 ++++--
 src/frontend/translate/translate_arm/translate_arm.h | 4 ++--
 3 files changed, 8 insertions(+), 6 deletions(-)

diff --git a/src/frontend/decoder/vfp2.h b/src/frontend/decoder/vfp2.h
index d3aa110f..8868164f 100644
--- a/src/frontend/decoder/vfp2.h
+++ b/src/frontend/decoder/vfp2.h
@@ -89,8 +89,6 @@ boost::optional<const VFP2Matcher<V>&> DecodeVFP2(u32 instruction) {
     INST(&V::vfp2_VABS,           "VABS",                    "cccc11101D110000dddd101z11M0mmmm"),
     INST(&V::vfp2_VNEG,           "VNEG",                    "cccc11101D110001dddd101z01M0mmmm"),
     INST(&V::vfp2_VSQRT,          "VSQRT",                   "cccc11101D110001dddd101z11M0mmmm"),
-    INST(&V::vfp2_VPUSH,          "VPUSH",                   "cccc11010D101101dddd101zvvvvvvvv"),
-    INST(&V::vfp2_VPOP,           "VPOP",                    "cccc11001D111101dddd101zvvvvvvvv"),
     // VCMP
     // VCMPE
     // VCVT
@@ -100,6 +98,8 @@ boost::optional<const VFP2Matcher<V>&> DecodeVFP2(u32 instruction) {
     // VSTR
     // VSTM
     // VSTMDB
+    INST(&V::vfp2_VPUSH,          "VPUSH",                   "cccc11010D101101dddd101zvvvvvvvv"),
+    INST(&V::vfp2_VPOP,           "VPOP",                    "cccc11001D111101dddd101zvvvvvvvv"),
     INST(&V::vfp2_VLDR,           "VLDR",                    "cccc1101UD01nnnndddd101zvvvvvvvv"),
     INST(&V::vfp2_VSTR,           "VSTR",                    "cccc1101UD00nnnndddd101zvvvvvvvv"),
     // VLDM
diff --git a/src/frontend/disassembler/disassembler_arm.cpp b/src/frontend/disassembler/disassembler_arm.cpp
index 41111a8c..1c9a0320 100644
--- a/src/frontend/disassembler/disassembler_arm.cpp
+++ b/src/frontend/disassembler/disassembler_arm.cpp
@@ -876,11 +876,11 @@ public:
         return Common::StringFromFormat("vsqrt%s.%s %s, %s", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D).c_str(), FPRegStr(sz, Vm, M).c_str());
     }
 
-    std::string  vfp2_VPOP(Cond cond, bool D, size_t Vd, bool sz, Imm8 imm8) {
+    std::string vfp2_VPOP(Cond cond, bool D, size_t Vd, bool sz, Imm8 imm8) {
         return Common::StringFromFormat("vpop%s %s(+%u)", CondToString(cond), FPRegStr(sz, Vd, D).c_str(), imm8 >> (sz ? 1 : 0));
     }
 
-    std::string  vfp2_VPUSH(Cond cond, bool D, size_t Vd, bool sz, Imm8 imm8) {
+    std::string vfp2_VPUSH(Cond cond, bool D, size_t Vd, bool sz, Imm8 imm8) {
         return Common::StringFromFormat("vpush%s %s(+%u)", CondToString(cond), FPRegStr(sz, Vd, D).c_str(), imm8 >> (sz ? 1 : 0));
     }
 
@@ -893,6 +893,8 @@ public:
         u32 imm32 = imm8 << 2;
         return Common::StringFromFormat("vstr%s %s, [%s, #%c%u]", CondToString(cond), FPRegStr(sz, Vd, D).c_str(), RegToString(n), U ? '+' : '-', imm32);
     }
+
+
 };
 
 std::string DisassembleArm(u32 instruction) {
diff --git a/src/frontend/translate/translate_arm/translate_arm.h b/src/frontend/translate/translate_arm/translate_arm.h
index 74cb7186..1da0b69f 100644
--- a/src/frontend/translate/translate_arm/translate_arm.h
+++ b/src/frontend/translate/translate_arm/translate_arm.h
@@ -357,12 +357,12 @@ struct ArmTranslatorVisitor final {
     bool vfp2_VABS(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm);
     bool vfp2_VNEG(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm);
     bool vfp2_VSQRT(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm);
-    bool vfp2_VPOP(Cond cond, bool D, size_t Vd, bool sz, Imm8 imm8);
-    bool vfp2_VPUSH(Cond cond, bool D, size_t Vd, bool sz, Imm8 imm8);
 
     // Floating-point load-store instructions
     bool vfp2_VLDR(Cond cond, bool U, bool D, Reg n, size_t Vd, bool sz, Imm8 imm8);
     bool vfp2_VSTR(Cond cond, bool U, bool D, Reg n, size_t Vd, bool sz, Imm8 imm8);
+    bool vfp2_VPOP(Cond cond, bool D, size_t Vd, bool sz, Imm8 imm8);
+    bool vfp2_VPUSH(Cond cond, bool D, size_t Vd, bool sz, Imm8 imm8);
 };
 
 } // namespace Arm