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A64: Implement LDR (literal, SIMD&FP)

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Lioncash 2018-05-14 09:12:56 -04:00 committed by MerryMage
parent 0da5e949a8
commit 9054d1c20b
2 changed files with 19 additions and 1 deletions
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2
src/frontend/A64/decoder/a64.inc
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@ -156,7 +156,7 @@ INST(LDAR, "LDARB, LDARH, LDAR", "zz001
INST(LDR_lit_gen, "LDR (literal)", "0z011000iiiiiiiiiiiiiiiiiiittttt") INST(LDR_lit_gen, "LDR (literal)", "0z011000iiiiiiiiiiiiiiiiiiittttt")
INST(LDRSW_lit, "LDRSW (literal)", "10011000iiiiiiiiiiiiiiiiiiittttt") INST(LDRSW_lit, "LDRSW (literal)", "10011000iiiiiiiiiiiiiiiiiiittttt")
INST(PRFM_lit, "PRFM (literal)", "11011000iiiiiiiiiiiiiiiiiiittttt") INST(PRFM_lit, "PRFM (literal)", "11011000iiiiiiiiiiiiiiiiiiittttt")
//INST(LDR_lit_fpsimd, "LDR (literal, SIMD&FP)", "oo011100iiiiiiiiiiiiiiiiiiittttt") INST(LDR_lit_fpsimd, "LDR (literal, SIMD&FP)", "oo011100iiiiiiiiiiiiiiiiiiittttt")
// Loads and stores - Load/Store no-allocate pair // Loads and stores - Load/Store no-allocate pair
//INST(STNP_gen, "STNP", "-010100000iiiiiiiuuuuunnnnnttttt") //INST(STNP_gen, "STNP", "-010100000iiiiiiiuuuuunnnnnttttt")

18
src/frontend/A64/translate/impl/load_store_load_literal.cpp
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@ -20,6 +20,24 @@ bool TranslatorVisitor::LDR_lit_gen(bool opc_0, Imm<19> imm19, Reg Rt) {
return true; return true;
} }
bool TranslatorVisitor::LDR_lit_fpsimd(Imm<2> opc, Imm<19> imm19, Vec Vt) {
if (opc == 0b11) {
return UnallocatedEncoding();
}
const u64 size = 4 << opc.ZeroExtend();
const u64 offset = imm19.SignExtend<u64>() << 2;
const IR::U64 address = ir.Imm64(ir.PC() + offset);
const IR::UAnyU128 data = Mem(address, size, AccType::VEC);
if (size == 16) {
V(128, Vt, data);
} else {
V(128, Vt, ir.ZeroExtendToQuad(data));
}
return true;
}
bool TranslatorVisitor::LDRSW_lit(Imm<19> imm19, Reg Rt) { bool TranslatorVisitor::LDRSW_lit(Imm<19> imm19, Reg Rt) {
s64 offset = concatenate(imm19, Imm<2>{0}).SignExtend<s64>(); s64 offset = concatenate(imm19, Imm<2>{0}).SignExtend<s64>();