From 998aef07f684e66e410ba27a2ec1cc82a4581278 Mon Sep 17 00:00:00 2001 From: Lioncash Date: Fri, 11 May 2018 09:34:49 -0400 Subject: [PATCH] A64: Implement SRSHR (scalar) --- src/frontend/A64/decoder/a64.inc | 2 +- .../impl/simd_scalar_shift_by_immediate.cpp | 16 ++++++++++++++++ 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc index 09115df6..32517e72 100644 --- a/src/frontend/A64/decoder/a64.inc +++ b/src/frontend/A64/decoder/a64.inc @@ -470,7 +470,7 @@ INST(CMEQ_reg_1, "CMEQ (register)", "01111 // Data Processing - FP and SIMD - SIMD Scalar shift by immediate INST(SSHR_1, "SSHR", "010111110IIIIiii000001nnnnnddddd") INST(SSRA_1, "SSRA", "010111110IIIIiii000101nnnnnddddd") -//INST(SRSHR_1, "SRSHR", "010111110IIIIiii001001nnnnnddddd") +INST(SRSHR_1, "SRSHR", "010111110IIIIiii001001nnnnnddddd") //INST(SRSRA_1, "SRSRA", "010111110IIIIiii001101nnnnnddddd") INST(SHL_1, "SHL", "010111110IIIIiii010101nnnnnddddd") //INST(SQSHL_imm_1, "SQSHL (immediate)", "010111110IIIIiii011101nnnnnddddd") diff --git a/src/frontend/A64/translate/impl/simd_scalar_shift_by_immediate.cpp b/src/frontend/A64/translate/impl/simd_scalar_shift_by_immediate.cpp index 3b39a381..766c46af 100644 --- a/src/frontend/A64/translate/impl/simd_scalar_shift_by_immediate.cpp +++ b/src/frontend/A64/translate/impl/simd_scalar_shift_by_immediate.cpp @@ -97,6 +97,22 @@ bool TranslatorVisitor::SRI_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { return true; } +bool TranslatorVisitor::SRSHR_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { + if (!immh.Bit<3>()) { + return ReservedValue(); + } + + const size_t esize = 64; + const u8 shift_amount = static_cast((esize * 2) - concatenate(immh, immb).ZeroExtend()); + + const IR::U64 operand = V_scalar(esize, Vn); + const IR::U64 round_bit = ir.LogicalShiftRight(ir.LogicalShiftLeft(operand, ir.Imm8(64 - shift_amount)), ir.Imm8(63)); + const IR::U64 result = ir.Add(ir.ArithmeticShiftRight(operand, ir.Imm8(shift_amount)), round_bit); + + V_scalar(esize, Vd, result); + return true; +} + bool TranslatorVisitor::SSHR_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { if (!immh.Bit<3>()) { return ReservedValue();