diff --git a/src/frontend/A32/decoder/asimd.inc b/src/frontend/A32/decoder/asimd.inc index 6ff00de6..5ce0c56b 100644 --- a/src/frontend/A32/decoder/asimd.inc +++ b/src/frontend/A32/decoder/asimd.inc @@ -55,10 +55,10 @@ INST(asimd_VRSQRTS, "VRSQRTS", "111100100D1znnnndddd111 // Two registers and a scalar INST(arm_UDF, "UNALLOCATED", "1111001-1-11-------------1-0----") // ASIMD INST(asimd_VMLA_scalar, "VMLA (scalar)", "1111001Q1Dzznnnndddd0o0FN1M0mmmm") // ASIMD -//INST(asimd_VMLAL_scalar, "VMLAL (scalar)", "1111001U1-BB--------0x10-1-0----") // ASIMD +INST(asimd_VMLAL_scalar, "VMLAL (scalar)", "1111001U1dzznnnndddd0o10N1M0mmmm") // ASIMD //INST(asimd_VQDMLAL, "VQDMLAL/VQDMLSL", "111100101-BB--------0x11-1-0----") // ASIMD INST(asimd_VMUL_scalar, "VMUL (scalar)", "1111001Q1Dzznnnndddd100FN1M0mmmm") // ASIMD -//INST(asimd_VMULL_scalar, "VMULL (scalar)", "1111001U1-BB--------1010-1-0----") // ASIMD +INST(asimd_VMULL_scalar, "VMULL (scalar)", "1111001U1Dzznnnndddd1010N1M0mmmm") // ASIMD //INST(asimd_VQDMULL, "VQDMULL", "111100101-BB--------1011-1-0----") // ASIMD //INST(asimd_VQDMULH, "VQDMULH", "1111001U1-BB--------1100-1-0----") // ASIMD //INST(asimd_VQRDMULH, "VQRDMULH", "1111001U1-BB--------1101-1-0----") // ASIMD diff --git a/src/frontend/A32/translate/impl/asimd_two_regs_scalar.cpp b/src/frontend/A32/translate/impl/asimd_two_regs_scalar.cpp index c73d7ed7..1939be1e 100644 --- a/src/frontend/A32/translate/impl/asimd_two_regs_scalar.cpp +++ b/src/frontend/A32/translate/impl/asimd_two_regs_scalar.cpp @@ -3,6 +3,8 @@ * SPDX-License-Identifier: 0BSD */ +#include + #include "common/assert.h" #include "common/bit_util.h" @@ -10,6 +12,12 @@ namespace Dynarmic::A32 { namespace { +std::pair GetScalarLocation(size_t esize, bool M, size_t Vm) { + const ExtReg m = ExtReg::Q0 + ((Vm >> 1) & (esize == 16 ? 0b11 : 0b111)); + const size_t index = concatenate(Imm<1>{Common::Bit<0>(Vm)}, Imm<1>{M}, Imm<1>{Common::Bit<3>(Vm)}).ZeroExtend() >> (esize == 16 ? 0 : 1); + return std::make_pair(m, index); +} + enum class MultiplyBehavior { Multiply, MultiplyAccumulate, @@ -30,11 +38,9 @@ bool ScalarMultiply(ArmTranslatorVisitor& v, bool Q, bool D, size_t sz, size_t V const size_t esize = 8U << sz; const auto d = ToVector(Q, Vd, D); const auto n = ToVector(Q, Vn, N); + const auto [m, index] = GetScalarLocation(esize, M, Vm); - const auto m = ExtReg::Q0 + ((Vm >> 1) & (esize == 16 ? 0b11 : 0b111)); - const auto index = concatenate(Imm<1>{Common::Bit<0>(Vm)}, Imm<1>{M}, Imm<1>{Common::Bit<3>(Vm)}).ZeroExtend() >> (esize == 16 ? 0 : 1); const auto scalar = v.ir.VectorGetElement(esize, v.ir.GetVector(m), index); - const auto reg_n = v.ir.GetVector(n); const auto reg_m = v.ir.VectorBroadcast(esize, scalar); const auto addend = F ? v.ir.FPVectorMul(esize, reg_n, reg_m, false) @@ -57,6 +63,40 @@ bool ScalarMultiply(ArmTranslatorVisitor& v, bool Q, bool D, size_t sz, size_t V v.ir.SetVector(d, result); return true; } + +bool ScalarMultiplyLong(ArmTranslatorVisitor& v, bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool M, size_t Vm, MultiplyBehavior multiply) { + ASSERT_MSG(sz != 0b11, "Decode error"); + if (sz == 0b00 || Common::Bit<0>(Vd)) { + return v.UndefinedInstruction(); + } + + const size_t esize = 8U << sz; + const auto d = ToVector(true, Vd, D); + const auto n = ToVector(false, Vn, N); + const auto [m, index] = GetScalarLocation(esize, M, Vm); + + const auto scalar = v.ir.VectorGetElement(esize, v.ir.GetVector(m), index); + const auto ext_scalar = U ? (esize == 16 ? IR::U32U64{v.ir.ZeroExtendToWord(scalar)} : IR::U32U64{v.ir.ZeroExtendToLong(scalar)}) + : (esize == 16 ? IR::U32U64{v.ir.SignExtendToWord(scalar)} : IR::U32U64{v.ir.SignExtendToLong(scalar)}); + const auto reg_n = U ? v.ir.VectorZeroExtend(esize, v.ir.GetVector(n)) : v.ir.VectorSignExtend(esize, v.ir.GetVector(n)); + const auto reg_m = v.ir.VectorBroadcast(esize * 2, ext_scalar); + const auto addend = v.ir.VectorMultiply(esize * 2, reg_n, reg_m); + const auto result = [&] { + switch (multiply) { + case MultiplyBehavior::Multiply: + return addend; + case MultiplyBehavior::MultiplyAccumulate: + return v.ir.VectorAdd(esize * 2, v.ir.GetVector(d), addend); + case MultiplyBehavior::MultiplySubtract: + return v.ir.VectorSub(esize * 2, v.ir.GetVector(d), addend); + default: + return IR::U128{}; + } + }(); + + v.ir.SetVector(d, result); + return true; +} } // Anonymous namespace bool ArmTranslatorVisitor::asimd_VMLA_scalar(bool Q, bool D, size_t sz, size_t Vn, size_t Vd, bool op, bool F, bool N, bool M, size_t Vm) { @@ -65,8 +105,18 @@ bool ArmTranslatorVisitor::asimd_VMLA_scalar(bool Q, bool D, size_t sz, size_t V return ScalarMultiply(*this, Q, D, sz, Vn, Vd, F, N, M, Vm, behavior); } +bool ArmTranslatorVisitor::asimd_VMLAL_scalar(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool op, bool N, bool M, size_t Vm) { + const auto behavior = op ? MultiplyBehavior::MultiplySubtract + : MultiplyBehavior::MultiplyAccumulate; + return ScalarMultiplyLong(*this, U, D, sz, Vn, Vd, N, M, Vm, behavior); +} + bool ArmTranslatorVisitor::asimd_VMUL_scalar(bool Q, bool D, size_t sz, size_t Vn, size_t Vd, bool F, bool N, bool M, size_t Vm) { return ScalarMultiply(*this, Q, D, sz, Vn, Vd, F, N, M, Vm, MultiplyBehavior::Multiply); } +bool ArmTranslatorVisitor::asimd_VMULL_scalar(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool M, size_t Vm) { + return ScalarMultiplyLong(*this, U, D, sz, Vn, Vd, N, M, Vm, MultiplyBehavior::Multiply); +} + } // namespace Dynarmic::A32 diff --git a/src/frontend/A32/translate/impl/translate_arm.h b/src/frontend/A32/translate/impl/translate_arm.h index ea4db9eb..940a88f9 100644 --- a/src/frontend/A32/translate/impl/translate_arm.h +++ b/src/frontend/A32/translate/impl/translate_arm.h @@ -496,7 +496,9 @@ struct ArmTranslatorVisitor final { // Advanced SIMD two registers and a scalar bool asimd_VMLA_scalar(bool Q, bool D, size_t sz, size_t Vn, size_t Vd, bool op, bool F, bool N, bool M, size_t Vm); + bool asimd_VMLAL_scalar(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool op, bool N, bool M, size_t Vm); bool asimd_VMUL_scalar(bool Q, bool D, size_t sz, size_t Vn, size_t Vd, bool F, bool N, bool M, size_t Vm); + bool asimd_VMULL_scalar(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool M, size_t Vm); // Two registers and a shift amount bool asimd_SHR(bool U, bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm);