From 9d8599190607e4898bc7b1c42193f4cf90390814 Mon Sep 17 00:00:00 2001 From: MerryMage Date: Tue, 13 Feb 2018 18:20:18 +0000 Subject: [PATCH] A64: Implement CMHI, CMHS --- src/frontend/A64/decoder/a64.inc | 4 +-- .../A64/translate/impl/simd_three_same.cpp | 28 +++++++++++++++++++ 2 files changed, 30 insertions(+), 2 deletions(-) diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc index 6a16b314..1a382d81 100644 --- a/src/frontend/A64/decoder/a64.inc +++ b/src/frontend/A64/decoder/a64.inc @@ -748,8 +748,8 @@ INST(ORN_asimd, "ORN (vector)", "0Q001 //INST(URHADD, "URHADD", "0Q101110zz1mmmmm000101nnnnnddddd") //INST(UHSUB, "UHSUB", "0Q101110zz1mmmmm001001nnnnnddddd") //INST(UQSUB_2, "UQSUB", "0Q101110zz1mmmmm001011nnnnnddddd") -//INST(CMHI_2, "CMHI (register)", "0Q101110zz1mmmmm001101nnnnnddddd") -//INST(CMHS_2, "CMHS (register)", "0Q101110zz1mmmmm001111nnnnnddddd") +INST(CMHI_2, "CMHI (register)", "0Q101110zz1mmmmm001101nnnnnddddd") +INST(CMHS_2, "CMHS (register)", "0Q101110zz1mmmmm001111nnnnnddddd") //INST(USHL_2, "USHL", "0Q101110zz1mmmmm010001nnnnnddddd") //INST(UQSHL_reg_2, "UQSHL (register)", "0Q101110zz1mmmmm010011nnnnnddddd") //INST(URSHL_2, "URSHL", "0Q101110zz1mmmmm010101nnnnnddddd") diff --git a/src/frontend/A64/translate/impl/simd_three_same.cpp b/src/frontend/A64/translate/impl/simd_three_same.cpp index b5ee5748..1a19b4ad 100644 --- a/src/frontend/A64/translate/impl/simd_three_same.cpp +++ b/src/frontend/A64/translate/impl/simd_three_same.cpp @@ -153,6 +153,34 @@ bool TranslatorVisitor::BIC_asimd_reg(bool Q, Vec Vm, Vec Vn, Vec Vd) { return true; } +bool TranslatorVisitor::CMHI_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { + if (size == 0b11 && !Q) { + return ReservedValue(); + } + const size_t esize = 8 << size.ZeroExtend(); + const size_t datasize = Q ? 128 : 64; + + const IR::U128 operand1 = V(datasize, Vn); + const IR::U128 operand2 = V(datasize, Vm); + const IR::U128 result = ir.VectorGreaterUnsigned(esize, operand1, operand2); + V(datasize, Vd, result); + return true; +} + +bool TranslatorVisitor::CMHS_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { + if (size == 0b11 && !Q) { + return ReservedValue(); + } + const size_t esize = 8 << size.ZeroExtend(); + const size_t datasize = Q ? 128 : 64; + + const IR::U128 operand1 = V(datasize, Vn); + const IR::U128 operand2 = V(datasize, Vm); + const IR::U128 result = ir.VectorGreaterEqualUnsigned(esize, operand1, operand2); + V(datasize, Vd, result); + return true; +} + bool TranslatorVisitor::UMAX(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { if (size == 0b11) { return ReservedValue();