From a8efe3f0f5ad148350c84d8c47275f9af28be6bf Mon Sep 17 00:00:00 2001 From: Lioncash Date: Sat, 20 Jun 2020 17:49:49 -0400 Subject: [PATCH] A32: Implement ASIMD VACGE/VACGT --- src/frontend/A32/decoder/asimd.inc | 2 +- src/frontend/A32/translate/impl/asimd_three_same.cpp | 11 +++++++++++ src/frontend/A32/translate/impl/translate_arm.h | 1 + 3 files changed, 13 insertions(+), 1 deletion(-) diff --git a/src/frontend/A32/decoder/asimd.inc b/src/frontend/A32/decoder/asimd.inc index 55b6bc7d..43df7118 100644 --- a/src/frontend/A32/decoder/asimd.inc +++ b/src/frontend/A32/decoder/asimd.inc @@ -44,7 +44,7 @@ INST(asimd_VMUL_float, "VMUL (floating-point)", "111100110D0znnnndddd110 INST(asimd_VCEQ_reg_float, "VCEQ (register)", "111100100D0znnnndddd1110NQM0mmmm") // ASIMD INST(asimd_VCGE_reg_float, "VCGE (register)", "111100110D0znnnndddd1110NQM0mmmm") // ASIMD INST(asimd_VCGT_reg_float, "VCGT (register)", "111100110D1znnnndddd1110NQM0mmmm") // ASIMD -//INST(asimd_VACGE, "VACGE", "111100110-CC--------1110---1----") // ASIMD +INST(asimd_VACGE, "VACGE", "111100110Doznnnndddd1110NQM1mmmm") // ASIMD INST(asimd_VMAX_float, "VMAX (floating-point)", "111100100D0znnnndddd1111NQM0mmmm") // ASIMD INST(asimd_VMIN_float, "VMIN (floating-point)", "111100100D1znnnndddd1111NQM0mmmm") // ASIMD INST(asimd_VRECPS, "VRECPS", "111100100D0znnnndddd1111NQM1mmmm") // ASIMD diff --git a/src/frontend/A32/translate/impl/asimd_three_same.cpp b/src/frontend/A32/translate/impl/asimd_three_same.cpp index 59ae1fad..61f4616f 100644 --- a/src/frontend/A32/translate/impl/asimd_three_same.cpp +++ b/src/frontend/A32/translate/impl/asimd_three_same.cpp @@ -13,6 +13,8 @@ enum class Comparison { GE, GT, EQ, + AbsoluteGE, + AbsoluteGT, }; template @@ -124,6 +126,10 @@ bool FloatComparison(ArmTranslatorVisitor& v, bool D, bool sz, size_t Vn, size_t return v.ir.FPVectorGreater(32, reg_n, reg_m, false); case Comparison::EQ: return v.ir.FPVectorEqual(32, reg_n, reg_m, false); + case Comparison::AbsoluteGE: + return v.ir.FPVectorGreaterEqual(32, v.ir.FPVectorAbs(32, reg_n), v.ir.FPVectorAbs(32, reg_m), false); + case Comparison::AbsoluteGT: + return v.ir.FPVectorGreater(32, v.ir.FPVectorAbs(32, reg_n), v.ir.FPVectorAbs(32, reg_m), false); default: return IR::U128{}; } @@ -573,6 +579,11 @@ bool ArmTranslatorVisitor::asimd_VCGT_reg_float(bool D, bool sz, size_t Vn, size return FloatComparison(*this, D, sz, Vn, Vd, N, Q, M, Vm, Comparison::GT); } +bool ArmTranslatorVisitor::asimd_VACGE(bool D, bool op, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) { + const auto comparison = op ? Comparison::AbsoluteGT : Comparison::AbsoluteGE; + return FloatComparison(*this, D, sz, Vn, Vd, N, Q, M, Vm, comparison); +} + bool ArmTranslatorVisitor::asimd_VMAX_float(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) { return FloatingPointInstruction(*this, D, sz, Vn, Vd, N, Q, M, Vm, [this](const auto&, const auto& reg_n, const auto& reg_m) { return ir.FPVectorMax(32, reg_n, reg_m, false); diff --git a/src/frontend/A32/translate/impl/translate_arm.h b/src/frontend/A32/translate/impl/translate_arm.h index 036b3ee3..666d8be9 100644 --- a/src/frontend/A32/translate/impl/translate_arm.h +++ b/src/frontend/A32/translate/impl/translate_arm.h @@ -486,6 +486,7 @@ struct ArmTranslatorVisitor final { bool asimd_VCEQ_reg_float(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm); bool asimd_VCGE_reg_float(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm); bool asimd_VCGT_reg_float(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm); + bool asimd_VACGE(bool D, bool op, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm); bool asimd_VMAX_float(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm); bool asimd_VMIN_float(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm); bool asimd_VRECPS(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);