diff --git a/src/dynarmic/frontend/A32/decoder/asimd.inc b/src/dynarmic/frontend/A32/decoder/asimd.inc
index 635df8e3..d943b22c 100644
--- a/src/dynarmic/frontend/A32/decoder/asimd.inc
+++ b/src/dynarmic/frontend/A32/decoder/asimd.inc
@@ -146,7 +146,7 @@ INST(v8_AESIMC,             "AESIMC",                   "111100111D11zz00dddd001
 INST(arm_UDF,               "UNALLOCATED",              "111100111-11--01----001010-0----") // v8
 INST(arm_UDF,               "UNALLOCATED (SHA1H)",      "111100111-11--01----001011-0----") // v8
 INST(arm_UDF,               "UNALLOCATED (SHA1SU1)",    "111100111-11--10----001110-0----") // v8
-INST(arm_UDF,               "UNALLOCATED (SHA256SU0)",  "111100111-11--10----001111-0----") // v8
+INST(v8_SHA256SU0,          "SHA256SU0",                "111100111D11zz10dddd001111M0mmmm") // v8
 
 // One register and modified immediate
 INST(asimd_VMOV_imm,        "VBIC, VMOV, VMVN, VORR (immediate)",  "1111001a1D000bcdVVVVmmmm0Qo1efgh") // ASIMD
diff --git a/src/dynarmic/frontend/A32/translate/impl/a32_translate_impl.h b/src/dynarmic/frontend/A32/translate/impl/a32_translate_impl.h
index 56ad5c1b..f588a003 100644
--- a/src/dynarmic/frontend/A32/translate/impl/a32_translate_impl.h
+++ b/src/dynarmic/frontend/A32/translate/impl/a32_translate_impl.h
@@ -920,6 +920,7 @@ struct TranslatorVisitor final {
     bool v8_AESE(bool D, size_t sz, size_t Vd, bool M, size_t Vm);
     bool v8_AESIMC(bool D, size_t sz, size_t Vd, bool M, size_t Vm);
     bool v8_AESMC(bool D, size_t sz, size_t Vd, bool M, size_t Vm);
+    bool v8_SHA256SU0(bool D, size_t sz, size_t Vd, bool M, size_t Vm);
     bool asimd_VCLS(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm);
     bool asimd_VCLZ(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm);
     bool asimd_VCNT(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm);
diff --git a/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_misc.cpp b/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_misc.cpp
index 20807ce2..e9532aa8 100644
--- a/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_misc.cpp
+++ b/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_misc.cpp
@@ -225,6 +225,21 @@ bool TranslatorVisitor::v8_AESMC(bool D, size_t sz, size_t Vd, bool M, size_t Vm
     return true;
 }
 
+bool TranslatorVisitor::v8_SHA256SU0(bool D, size_t sz, size_t Vd, bool M, size_t Vm) {
+    if (sz != 0b10 || Common::Bit<0>(Vd) || Common::Bit<0>(Vm)) {
+        return UndefinedInstruction();
+    }
+
+    const auto d = ToVector(true, Vd, D);
+    const auto m = ToVector(true, Vm, M);
+    const auto x = ir.GetVector(d);
+    const auto y = ir.GetVector(m);
+    const auto result = ir.SHA256MessageSchedule0(x, y);
+
+    ir.SetVector(d, result);
+    return true;
+}
+
 bool TranslatorVisitor::asimd_VCLS(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm) {
     if (sz == 0b11) {
         return UndefinedInstruction();