From ad6a04c5847e81b2479d8610ff01b2927286d484 Mon Sep 17 00:00:00 2001
From: Macdu <Macdu@users.noreply.github.com>
Date: Tue, 18 Oct 2022 00:29:47 +0200
Subject: [PATCH] backend/arm64: FPVectorToHalf32 implementation

---
 .../arm64/emit_arm64_vector_floating_point.cpp  | 17 +++++++++++++----
 1 file changed, 13 insertions(+), 4 deletions(-)

diff --git a/src/dynarmic/backend/arm64/emit_arm64_vector_floating_point.cpp b/src/dynarmic/backend/arm64/emit_arm64_vector_floating_point.cpp
index 22964daf..9f632c24 100644
--- a/src/dynarmic/backend/arm64/emit_arm64_vector_floating_point.cpp
+++ b/src/dynarmic/backend/arm64/emit_arm64_vector_floating_point.cpp
@@ -630,10 +630,19 @@ void EmitIR<IR::Opcode::FPVectorSub64>(oaknut::CodeGenerator& code, EmitContext&
 
 template<>
 void EmitIR<IR::Opcode::FPVectorToHalf32>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
-    (void)code;
-    (void)ctx;
-    (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
+    const auto rounding_mode = static_cast<FP::RoundingMode>(args[1].GetImmediateU8());
+    ASSERT(rounding_mode == FP::RoundingMode::ToNearest_TieEven);
+    const bool fpcr_controlled = args[2].GetImmediateU1();
+
+    auto Dresult = ctx.reg_alloc.WriteD(inst);
+    auto Qoperand = ctx.reg_alloc.ReadQ(args[0]);
+    RegAlloc::Realize(Dresult, Qoperand);
+    ctx.fpsr.Load();
+
+    MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&] {
+        code.FCVTN(Dresult->H4(), Qoperand->S4());
+    });
 }
 
 template<>