From b1df70578f1ead4c0a32d7c9e0230ea86cceb5f9 Mon Sep 17 00:00:00 2001 From: MerryMage Date: Wed, 21 Dec 2016 14:15:46 +0000 Subject: [PATCH] fuzz_arm: Add test cases for saturation instructions --- tests/arm/fuzz_arm.cpp | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/tests/arm/fuzz_arm.cpp b/tests/arm/fuzz_arm.cpp index fad261d1..e9090955 100644 --- a/tests/arm/fuzz_arm.cpp +++ b/tests/arm/fuzz_arm.cpp @@ -806,8 +806,6 @@ TEST_CASE("Fuzz ARM reversal instructions", "[JitX64]") { } } - - TEST_CASE("Fuzz ARM extension instructions", "[JitX64]") { const auto is_valid = [](u32 instr) -> bool { // R15 as Rd or Rm is UNPREDICTABLE @@ -1092,7 +1090,7 @@ TEST_CASE("Test ARM misc instructions", "[JitX64]") { } } -TEST_CASE("Fuzz ARM saturated instructions", "[JitX64]") { +TEST_CASE("Fuzz ARM saturated add/sub instructions", "[JitX64]") { auto is_valid = [](u32 inst) -> bool { // R15 as Rd, Rn, or Rm is UNPREDICTABLE return Bits<16, 19>(inst) != 0b1111 && @@ -1114,6 +1112,24 @@ TEST_CASE("Fuzz ARM saturated instructions", "[JitX64]") { } } +TEST_CASE("Fuzz ARM saturation instructions", "[JitX64]") { + auto is_valid = [](u32 inst) -> bool { + // R15 as Rd or Rn is UNPREDICTABLE + return Bits<12, 15>(inst) != 0b1111 && + Bits<0, 3>(inst) != 0b1111; + }; + + const std::array instructions = {{ + InstructionGenerator("cccc0110101vvvvvddddvvvvvr01nnnn", is_valid), // SSAT + InstructionGenerator("cccc01101010vvvvdddd11110011nnnn", is_valid), // SSAT16 + InstructionGenerator("cccc0110111vvvvvddddvvvvvr01nnnn", is_valid), // USAT + InstructionGenerator("cccc01101110vvvvdddd11110011nnnn", is_valid), // USAT16 + }}; + + FuzzJitArm(4, 5, 10000, [&instructions]() -> u32 { + return instructions[RandInt(0, instructions.size() - 1)].Generate(); + }); +} TEST_CASE("Fuzz ARM packing instructions", "[JitX64]") { auto is_pkh_valid = [](u32 inst) -> bool {