diff --git a/src/backend/x64/a32_emit_x64.cpp b/src/backend/x64/a32_emit_x64.cpp
index 6f840821..d563ff50 100644
--- a/src/backend/x64/a32_emit_x64.cpp
+++ b/src/backend/x64/a32_emit_x64.cpp
@@ -748,7 +748,7 @@ void A32EmitX64::EmitA32SetFpscr(A32EmitContext& ctx, IR::Inst* inst) {
 
 void A32EmitX64::EmitA32GetFpscrNZCV(A32EmitContext& ctx, IR::Inst* inst) {
     const Xbyak::Reg32 result = ctx.reg_alloc.ScratchGpr().cvt32();
-    code.mov(result, dword[r15 + offsetof(A32JitState, FPSCR_nzcv)]);
+    code.mov(result, dword[r15 + offsetof(A32JitState, fpsr_nzcv)]);
     ctx.reg_alloc.DefineValue(inst, result);
 }
 
@@ -761,7 +761,7 @@ void A32EmitX64::EmitA32SetFpscrNZCV(A32EmitContext& ctx, IR::Inst* inst) {
     code.shl(value, 16);
     code.and_(value, 0xF0000000);
 
-    code.mov(dword[r15 + offsetof(A32JitState, FPSCR_nzcv)], value);
+    code.mov(dword[r15 + offsetof(A32JitState, fpsr_nzcv)], value);
 }
 
 void A32EmitX64::EmitA32ClearExclusive(A32EmitContext&, IR::Inst*) {
diff --git a/src/backend/x64/a32_interface.cpp b/src/backend/x64/a32_interface.cpp
index 215fa420..ca264b47 100644
--- a/src/backend/x64/a32_interface.cpp
+++ b/src/backend/x64/a32_interface.cpp
@@ -272,7 +272,7 @@ void TransferJitState(A32JitState& dest, const A32JitState& src, bool reset_rsb)
     dest.guest_MXCSR = src.guest_MXCSR;
     dest.fpsr_idc = src.fpsr_idc;
     dest.fpcr_mode = src.fpcr_mode;
-    dest.FPSCR_nzcv = src.FPSCR_nzcv;
+    dest.fpsr_nzcv = src.fpsr_nzcv;
     if (reset_rsb) {
         dest.ResetRSB();
     } else {
diff --git a/src/backend/x64/a32_jitstate.cpp b/src/backend/x64/a32_jitstate.cpp
index 746ae05f..c0ec554d 100644
--- a/src/backend/x64/a32_jitstate.cpp
+++ b/src/backend/x64/a32_jitstate.cpp
@@ -155,10 +155,10 @@ constexpr u32 FPSCR_NZCV_MASK = 0xF0000000;
 
 u32 A32JitState::Fpscr() const {
     ASSERT((fpcr_mode & ~FPSCR_MODE_MASK) == 0);
-    ASSERT((FPSCR_nzcv & ~FPSCR_NZCV_MASK) == 0);
+    ASSERT((fpsr_nzcv & ~FPSCR_NZCV_MASK) == 0);
     ASSERT((fpsr_idc & ~(1 << 7)) == 0);
 
-    u32 FPSCR = fpcr_mode | FPSCR_nzcv;
+    u32 FPSCR = fpcr_mode | fpsr_nzcv;
     FPSCR |= (guest_MXCSR & 0b0000000000001);       // IOC = IE
     FPSCR |= (guest_MXCSR & 0b0000000111100) >> 1;  // IXC, UFC, OFC, DZC = PE, UE, OE, ZE
     FPSCR |= fpsr_idc;
@@ -170,7 +170,7 @@ u32 A32JitState::Fpscr() const {
 void A32JitState::SetFpscr(u32 FPSCR) {
     old_FPSCR = FPSCR;
     fpcr_mode = FPSCR & FPSCR_MODE_MASK;
-    FPSCR_nzcv = FPSCR & FPSCR_NZCV_MASK;
+    fpsr_nzcv = FPSCR & FPSCR_NZCV_MASK;
     guest_MXCSR = 0;
 
     // Exception masks / enables
diff --git a/src/backend/x64/a32_jitstate.h b/src/backend/x64/a32_jitstate.h
index 29bed92d..af5bf47b 100644
--- a/src/backend/x64/a32_jitstate.h
+++ b/src/backend/x64/a32_jitstate.h
@@ -71,7 +71,7 @@ struct A32JitState {
     u32 fpsr_qc = 0; // Dummy value
     u32 fpsr_idc = 0;
     u32 fpcr_mode = 0;
-    u32 FPSCR_nzcv = 0;
+    u32 fpsr_nzcv = 0;
     u32 old_FPSCR = 0;
     u32 Fpscr() const;
     void SetFpscr(u32 FPSCR);