diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc index b0ab596f..4b63fd6d 100644 --- a/src/frontend/A64/decoder/a64.inc +++ b/src/frontend/A64/decoder/a64.inc @@ -610,7 +610,7 @@ INST(FRINTZ_2, "FRINTZ (vector)", "0Q001 INST(FCVTPS_4, "FCVTPS (vector)", "0Q0011101z100001101010nnnnnddddd") //INST(FCVTZS_int_3, "FCVTZS (vector, integer)", "0Q00111011111001101110nnnnnddddd") INST(FCVTZS_int_4, "FCVTZS (vector, integer)", "0Q0011101z100001101110nnnnnddddd") -//INST(URECPE, "URECPE", "0Q0011101z100001110010nnnnnddddd") +INST(URECPE, "URECPE", "0Q0011101z100001110010nnnnnddddd") //INST(FRECPE_3, "FRECPE", "0Q00111011111001110110nnnnnddddd") INST(FRECPE_4, "FRECPE", "0Q0011101z100001110110nnnnnddddd") INST(REV32_asimd, "REV32 (vector)", "0Q101110zz100000000010nnnnnddddd") diff --git a/src/frontend/A64/translate/impl/simd_two_register_misc.cpp b/src/frontend/A64/translate/impl/simd_two_register_misc.cpp index 7942f04f..f103ce16 100644 --- a/src/frontend/A64/translate/impl/simd_two_register_misc.cpp +++ b/src/frontend/A64/translate/impl/simd_two_register_misc.cpp @@ -645,6 +645,20 @@ bool TranslatorVisitor::UADDLP(bool Q, Imm<2> size, Vec Vn, Vec Vd) { return PairedAddLong(*this, Q, size, Vn, Vd, Signedness::Unsigned, PairedAddLongExtraBehavior::None); } +bool TranslatorVisitor::URECPE(bool Q, bool sz, Vec Vn, Vec Vd) { + if (sz) { + return ReservedValue(); + } + + const size_t datasize = Q ? 128 : 64; + + const IR::U128 operand = V(datasize, Vn); + const IR::U128 result = ir.VectorUnsignedRecipEstimate(operand); + + V(datasize, Vd, result); + return true; +} + bool TranslatorVisitor::SCVTF_int_4(bool Q, bool sz, Vec Vn, Vec Vd) { return IntegerConvertToFloat(*this, Q, sz, Vn, Vd, Signedness::Signed); }