From bd892ec4ef174e0f70f916dc6df3faa11be84451 Mon Sep 17 00:00:00 2001 From: Lioncash Date: Sat, 9 Mar 2019 17:36:00 -0500 Subject: [PATCH] frontend/ir/ir_emitter: Amend FPRecipExponent to handle half-precision floating point --- src/backend/x64/emit_x64_floating_point.cpp | 4 ++++ src/frontend/ir/ir_emitter.cpp | 13 ++++++++++--- src/frontend/ir/ir_emitter.h | 2 +- src/frontend/ir/microinstruction.cpp | 1 + src/frontend/ir/opcodes.inc | 1 + 5 files changed, 17 insertions(+), 4 deletions(-) diff --git a/src/backend/x64/emit_x64_floating_point.cpp b/src/backend/x64/emit_x64_floating_point.cpp index 88ceb413..028c281d 100644 --- a/src/backend/x64/emit_x64_floating_point.cpp +++ b/src/backend/x64/emit_x64_floating_point.cpp @@ -728,6 +728,10 @@ static void EmitFPRecipExponent(BlockOfCode& code, EmitContext& ctx, IR::Inst* i code.CallFunction(&FP::FPRecipExponent); } +void EmitX64::EmitFPRecipExponent16(EmitContext& ctx, IR::Inst* inst) { + EmitFPRecipExponent(code, ctx, inst); +} + void EmitX64::EmitFPRecipExponent32(EmitContext& ctx, IR::Inst* inst) { EmitFPRecipExponent(code, ctx, inst); } diff --git a/src/frontend/ir/ir_emitter.cpp b/src/frontend/ir/ir_emitter.cpp index 07b54308..35c8d07b 100644 --- a/src/frontend/ir/ir_emitter.cpp +++ b/src/frontend/ir/ir_emitter.cpp @@ -1895,11 +1895,18 @@ U32U64 IREmitter::FPRecipEstimate(const U32U64& a) { return Inst(Opcode::FPRecipEstimate64, a); } -U32U64 IREmitter::FPRecipExponent(const U32U64& a) { - if (a.GetType() == Type::U32) { +U16U32U64 IREmitter::FPRecipExponent(const U16U32U64& a) { + switch (a.GetType()) { + case Type::U16: + return Inst(Opcode::FPRecipExponent16, a); + case Type::U32: return Inst(Opcode::FPRecipExponent32, a); + case Type::U64: + return Inst(Opcode::FPRecipExponent64, a); + default: + UNREACHABLE(); + return U16U32U64{}; } - return Inst(Opcode::FPRecipExponent64, a); } U32U64 IREmitter::FPRecipStepFused(const U32U64& a, const U32U64& b) { diff --git a/src/frontend/ir/ir_emitter.h b/src/frontend/ir/ir_emitter.h index 8fb3cd57..0e29d716 100644 --- a/src/frontend/ir/ir_emitter.h +++ b/src/frontend/ir/ir_emitter.h @@ -305,7 +305,7 @@ public: U32U64 FPMulX(const U32U64& a, const U32U64& b); U32U64 FPNeg(const U32U64& a); U32U64 FPRecipEstimate(const U32U64& a); - U32U64 FPRecipExponent(const U32U64& a); + U16U32U64 FPRecipExponent(const U16U32U64& a); U32U64 FPRecipStepFused(const U32U64& a, const U32U64& b); U32U64 FPRoundInt(const U32U64& a, FP::RoundingMode rounding, bool exact); U32U64 FPRSqrtEstimate(const U32U64& a); diff --git a/src/frontend/ir/microinstruction.cpp b/src/frontend/ir/microinstruction.cpp index 10257e54..3055d2fd 100644 --- a/src/frontend/ir/microinstruction.cpp +++ b/src/frontend/ir/microinstruction.cpp @@ -273,6 +273,7 @@ bool Inst::ReadsFromAndWritesToFPSRCumulativeExceptionBits() const { case Opcode::FPMulAdd64: case Opcode::FPRecipEstimate32: case Opcode::FPRecipEstimate64: + case Opcode::FPRecipExponent16: case Opcode::FPRecipExponent32: case Opcode::FPRecipExponent64: case Opcode::FPRecipStepFused32: diff --git a/src/frontend/ir/opcodes.inc b/src/frontend/ir/opcodes.inc index 06b06e2c..ca87994a 100644 --- a/src/frontend/ir/opcodes.inc +++ b/src/frontend/ir/opcodes.inc @@ -486,6 +486,7 @@ OPCODE(FPNeg32, U32, U32 OPCODE(FPNeg64, U64, U64 ) OPCODE(FPRecipEstimate32, U32, U32 ) OPCODE(FPRecipEstimate64, U64, U64 ) +OPCODE(FPRecipExponent16, U16, U16 ) OPCODE(FPRecipExponent32, U32, U32 ) OPCODE(FPRecipExponent64, U64, U64 ) OPCODE(FPRecipStepFused32, U32, U32, U32 )