From bf093395d8f9173ce5ff9bcb58e271f570354a38 Mon Sep 17 00:00:00 2001 From: MerryMage Date: Sun, 21 Jun 2020 12:19:02 +0100 Subject: [PATCH] A32: Implement ASIMD VMOVN --- src/frontend/A32/decoder/asimd.inc | 2 +- .../A32/translate/impl/asimd_two_regs_misc.cpp | 15 +++++++++++++++ src/frontend/A32/translate/impl/translate_arm.h | 1 + 3 files changed, 17 insertions(+), 1 deletion(-) diff --git a/src/frontend/A32/decoder/asimd.inc b/src/frontend/A32/decoder/asimd.inc index 13f8f117..595a3a2d 100644 --- a/src/frontend/A32/decoder/asimd.inc +++ b/src/frontend/A32/decoder/asimd.inc @@ -102,7 +102,7 @@ INST(asimd_VSWP, "VSWP", "111100111D110010dddd000 INST(asimd_VTRN, "VTRN", "111100111D11zz10dddd00001QM0mmmm") // ASIMD INST(asimd_VUZP, "VUZP", "111100111D11zz10dddd00010QM0mmmm") // ASIMD INST(asimd_VZIP, "VZIP", "111100111D11zz10dddd00011QM0mmmm") // ASIMD -//INST(asimd_VMOVN, "VMOVN", "111100111-11--10----001000-0----") // ASIMD +INST(asimd_VMOVN, "VMOVN", "111100111D11zz10dddd001000M0mmmm") // ASIMD //INST(asimd_VQMOVUN, "VQMOVUN", "111100111-11--10----001001-0----") // ASIMD //INST(asimd_VQMOVN, "VQMOVN", "111100111-11--10----00101x-0----") // ASIMD //INST(asimd_VSHLL_max, "VSHLL_max", "111100111-11--10----001100-0----") // ASIMD diff --git a/src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp b/src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp index 24225a60..284b38b6 100644 --- a/src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp +++ b/src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp @@ -491,6 +491,21 @@ bool ArmTranslatorVisitor::asimd_VZIP(bool D, size_t sz, size_t Vd, bool Q, bool return true; } +bool ArmTranslatorVisitor::asimd_VMOVN(bool D, size_t sz, size_t Vd, bool M, size_t Vm) { + if (sz == 0b11 || Common::Bit<0>(Vm)) { + return UndefinedInstruction(); + } + const size_t esize = 8U << sz; + const auto d = ToVector(false, Vd, D); + const auto m = ToVector(true, Vm, M); + + const auto reg_m = ir.GetVector(m); + const auto result = ir.VectorNarrow(2 * esize, reg_m); + + ir.SetVector(d, result); + return true; +} + bool ArmTranslatorVisitor::asimd_VRECPE(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm) { if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) { return UndefinedInstruction(); diff --git a/src/frontend/A32/translate/impl/translate_arm.h b/src/frontend/A32/translate/impl/translate_arm.h index 6ad84db6..670c26fe 100644 --- a/src/frontend/A32/translate/impl/translate_arm.h +++ b/src/frontend/A32/translate/impl/translate_arm.h @@ -530,6 +530,7 @@ struct ArmTranslatorVisitor final { bool asimd_VTRN(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm); bool asimd_VUZP(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm); bool asimd_VZIP(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm); + bool asimd_VMOVN(bool D, size_t sz, size_t Vd, bool M, size_t Vm); bool asimd_VRECPE(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm); bool asimd_VRSQRTE(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm);