From 72af5a3dfff7431a5e6359ccba38b712202382e0 Mon Sep 17 00:00:00 2001 From: Lioncash Date: Wed, 20 Mar 2019 22:28:42 -0400 Subject: [PATCH 1/3] simd_scalar_x_indexed_element: Factor out index and Vm argument construction This will be useful in the implementations of SQRDMULH and SQDMULL{2} as well. --- src/frontend/A64/decoder/a64.inc | 2 +- .../impl/simd_scalar_x_indexed_element.cpp | 17 +++++++++-------- 2 files changed, 10 insertions(+), 9 deletions(-) diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc index 707f1a0d..8100daae 100644 --- a/src/frontend/A64/decoder/a64.inc +++ b/src/frontend/A64/decoder/a64.inc @@ -537,7 +537,7 @@ INST(FCVTZU_fix_1, "FCVTZU (vector, fixed-point)", "01111 //INST(SQDMLSL_elt_1, "SQDMLSL, SQDMLSL2 (by element)", "01011111zzLMmmmm0111H0nnnnnddddd") //INST(SQDMULL_elt_1, "SQDMULL, SQDMULL2 (by element)", "01011111zzLMmmmm1011H0nnnnnddddd") INST(SQDMULH_elt_1, "SQDMULH (by element)", "01011111zzLMmmmm1100H0nnnnnddddd") -//INST(SQRDMULH_elt_1, "SQRDMULH (by element)", "01011111zzLMmmmm1101H0nnnnnddddd") +INST(SQRDMULH_elt_1, "SQRDMULH (by element)", "01011111zzLMmmmm1101H0nnnnnddddd") //INST(FMLA_elt_1, "FMLA (by element)", "0101111100LMmmmm0001H0nnnnnddddd") INST(FMLA_elt_2, "FMLA (by element)", "010111111zLMmmmm0001H0nnnnnddddd") //INST(FMLS_elt_1, "FMLS (by element)", "0101111100LMmmmm0101H0nnnnnddddd") diff --git a/src/frontend/A64/translate/impl/simd_scalar_x_indexed_element.cpp b/src/frontend/A64/translate/impl/simd_scalar_x_indexed_element.cpp index fd799eec..b7eef081 100644 --- a/src/frontend/A64/translate/impl/simd_scalar_x_indexed_element.cpp +++ b/src/frontend/A64/translate/impl/simd_scalar_x_indexed_element.cpp @@ -9,6 +9,14 @@ namespace Dynarmic::A64 { namespace { +std::pair Combine(Imm<2> size, Imm<1> H, Imm<1> L, Imm<1> M, Imm<4> Vmlo) { + if (size == 0b01) { + return {concatenate(H, L, M).ZeroExtend(), Vmlo.ZeroExtend()}; + } + + return {concatenate(H, L).ZeroExtend(), concatenate(M, Vmlo).ZeroExtend()}; +} + enum class ExtraBehavior { None, Accumulate, @@ -74,14 +82,7 @@ bool TranslatorVisitor::SQDMULH_elt_1(Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vm } const size_t esize = 8 << size.ZeroExtend(); - const auto [index, Vmhi] = [=] { - if (size == 0b01) { - return std::make_pair(concatenate(H, L, M).ZeroExtend(), Imm<1>{0}); - } - - return std::make_pair(concatenate(H, L).ZeroExtend(), M); - }(); - const Vec Vm = concatenate(Vmhi, Vmlo).ZeroExtend(); + const auto [index, Vm] = Combine(size, H, L, M, Vmlo); const IR::UAny operand1 = V_scalar(esize, Vn); const IR::UAny operand2 = ir.VectorGetElement(esize, V(128, Vm), index); From 692aba91b6c155be89324e3e36f0ebb5b4fa7df8 Mon Sep 17 00:00:00 2001 From: Lioncash Date: Wed, 20 Mar 2019 22:30:37 -0400 Subject: [PATCH 2/3] A64: Implement SQDMULL{2}'s scalar indexed element variant --- src/frontend/A64/decoder/a64.inc | 4 ++-- src/frontend/A64/translate/impl/impl.h | 6 +++--- .../impl/simd_scalar_x_indexed_element.cpp | 17 +++++++++++++++++ 3 files changed, 22 insertions(+), 5 deletions(-) diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc index 8100daae..fa7453b6 100644 --- a/src/frontend/A64/decoder/a64.inc +++ b/src/frontend/A64/decoder/a64.inc @@ -535,9 +535,9 @@ INST(FCVTZU_fix_1, "FCVTZU (vector, fixed-point)", "01111 // Data Processing - FP and SIMD - SIMD Scalar x indexed element //INST(SQDMLAL_elt_1, "SQDMLAL, SQDMLAL2 (by element)", "01011111zzLMmmmm0011H0nnnnnddddd") //INST(SQDMLSL_elt_1, "SQDMLSL, SQDMLSL2 (by element)", "01011111zzLMmmmm0111H0nnnnnddddd") -//INST(SQDMULL_elt_1, "SQDMULL, SQDMULL2 (by element)", "01011111zzLMmmmm1011H0nnnnnddddd") +INST(SQDMULL_elt_1, "SQDMULL, SQDMULL2 (by element)", "01011111zzLMmmmm1011H0nnnnnddddd") INST(SQDMULH_elt_1, "SQDMULH (by element)", "01011111zzLMmmmm1100H0nnnnnddddd") -INST(SQRDMULH_elt_1, "SQRDMULH (by element)", "01011111zzLMmmmm1101H0nnnnnddddd") +//INST(SQRDMULH_elt_1, "SQRDMULH (by element)", "01011111zzLMmmmm1101H0nnnnnddddd") //INST(FMLA_elt_1, "FMLA (by element)", "0101111100LMmmmm0001H0nnnnnddddd") INST(FMLA_elt_2, "FMLA (by element)", "010111111zLMmmmm0001H0nnnnnddddd") //INST(FMLS_elt_1, "FMLS (by element)", "0101111100LMmmmm0101H0nnnnnddddd") diff --git a/src/frontend/A64/translate/impl/impl.h b/src/frontend/A64/translate/impl/impl.h index 1f502aa1..80fab7c0 100644 --- a/src/frontend/A64/translate/impl/impl.h +++ b/src/frontend/A64/translate/impl/impl.h @@ -642,9 +642,9 @@ struct TranslatorVisitor final { bool FCVTZU_fix_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd); // Data Processing - FP and SIMD - SIMD Scalar x indexed element - bool SQDMLAL_elt_1(Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Reg Rn, Vec Vd); - bool SQDMLSL_elt_1(Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Reg Rn, Vec Vd); - bool SQDMULL_elt_1(Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Reg Rn, Vec Vd); + bool SQDMLAL_elt_1(Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn, Vec Vd); + bool SQDMLSL_elt_1(Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn, Vec Vd); + bool SQDMULL_elt_1(Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn, Vec Vd); bool SQDMULH_elt_1(Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn, Vec Vd); bool SQRDMULH_elt_1(Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn, Vec Vd); bool FMLA_elt_1(Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn, Vec Vd); diff --git a/src/frontend/A64/translate/impl/simd_scalar_x_indexed_element.cpp b/src/frontend/A64/translate/impl/simd_scalar_x_indexed_element.cpp index b7eef081..6b5ab98e 100644 --- a/src/frontend/A64/translate/impl/simd_scalar_x_indexed_element.cpp +++ b/src/frontend/A64/translate/impl/simd_scalar_x_indexed_element.cpp @@ -94,4 +94,21 @@ bool TranslatorVisitor::SQDMULH_elt_1(Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vm return true; } +bool TranslatorVisitor::SQDMULL_elt_1(Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn, Vec Vd) { + if (size == 0b00 || size == 0b11) { + return UnallocatedEncoding(); + } + + const size_t esize = 8 << size.ZeroExtend(); + const auto [index, Vm] = Combine(size, H, L, M, Vmlo); + + const IR::U128 operand1 = ir.ZeroExtendToQuad(ir.VectorGetElement(esize, V(128, Vn), 0)); + const IR::UAny operand2 = ir.VectorGetElement(esize, V(128, Vm), index); + const IR::U128 broadcast = ir.VectorBroadcast(esize, operand2); + const IR::U128 result = ir.VectorSignedSaturatedDoublingMultiplyLong(esize, operand1, broadcast); + + V_scalar(esize * 2, Vd, result); + return true; +} + } // namespace Dynarmic::A64 From 97dd3d059647e7e1ff0ffbb3c3e8423bef75a897 Mon Sep 17 00:00:00 2001 From: Lioncash Date: Wed, 20 Mar 2019 23:26:55 -0400 Subject: [PATCH 3/3] A64: Implement SQRDMULH's scalar indexed element variant --- src/frontend/A64/decoder/a64.inc | 2 +- .../impl/simd_scalar_x_indexed_element.cpp | 20 ++++++++++++++++++- 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc index fa7453b6..60c2c179 100644 --- a/src/frontend/A64/decoder/a64.inc +++ b/src/frontend/A64/decoder/a64.inc @@ -537,7 +537,7 @@ INST(FCVTZU_fix_1, "FCVTZU (vector, fixed-point)", "01111 //INST(SQDMLSL_elt_1, "SQDMLSL, SQDMLSL2 (by element)", "01011111zzLMmmmm0111H0nnnnnddddd") INST(SQDMULL_elt_1, "SQDMULL, SQDMULL2 (by element)", "01011111zzLMmmmm1011H0nnnnnddddd") INST(SQDMULH_elt_1, "SQDMULH (by element)", "01011111zzLMmmmm1100H0nnnnnddddd") -//INST(SQRDMULH_elt_1, "SQRDMULH (by element)", "01011111zzLMmmmm1101H0nnnnnddddd") +INST(SQRDMULH_elt_1, "SQRDMULH (by element)", "01011111zzLMmmmm1101H0nnnnnddddd") //INST(FMLA_elt_1, "FMLA (by element)", "0101111100LMmmmm0001H0nnnnnddddd") INST(FMLA_elt_2, "FMLA (by element)", "010111111zLMmmmm0001H0nnnnnddddd") //INST(FMLS_elt_1, "FMLS (by element)", "0101111100LMmmmm0101H0nnnnnddddd") diff --git a/src/frontend/A64/translate/impl/simd_scalar_x_indexed_element.cpp b/src/frontend/A64/translate/impl/simd_scalar_x_indexed_element.cpp index 6b5ab98e..2f19f23a 100644 --- a/src/frontend/A64/translate/impl/simd_scalar_x_indexed_element.cpp +++ b/src/frontend/A64/translate/impl/simd_scalar_x_indexed_element.cpp @@ -94,6 +94,24 @@ bool TranslatorVisitor::SQDMULH_elt_1(Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vm return true; } +bool TranslatorVisitor::SQRDMULH_elt_1(Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn, Vec Vd) { + if (size == 0b00 || size == 0b11) { + return UnallocatedEncoding(); + } + + const size_t esize = 8 << size.ZeroExtend(); + const auto [index, Vm] = Combine(size, H, L, M, Vmlo); + + const IR::U128 operand1 = ir.ZeroExtendToQuad(ir.VectorGetElement(esize, V(128, Vn), 0)); + const IR::UAny operand2 = ir.VectorGetElement(esize, V(128, Vm), index); + const IR::U128 broadcast = ir.VectorBroadcast(esize, operand2); + const IR::UpperAndLower multiply = ir.VectorSignedSaturatedDoublingMultiply(esize, operand1, broadcast); + const IR::U128 result = ir.VectorAdd(esize, multiply.upper, ir.VectorLogicalShiftRight(esize, multiply.lower, static_cast(esize - 1))); + + V(128, Vd, result); + return true; +} + bool TranslatorVisitor::SQDMULL_elt_1(Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn, Vec Vd) { if (size == 0b00 || size == 0b11) { return UnallocatedEncoding(); @@ -107,7 +125,7 @@ bool TranslatorVisitor::SQDMULL_elt_1(Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vm const IR::U128 broadcast = ir.VectorBroadcast(esize, operand2); const IR::U128 result = ir.VectorSignedSaturatedDoublingMultiplyLong(esize, operand1, broadcast); - V_scalar(esize * 2, Vd, result); + V(128, Vd, result); return true; }