diff --git a/src/frontend/A32/translate/translate_arm/exception_generating.cpp b/src/frontend/A32/translate/translate_arm/exception_generating.cpp
index 87a37642..01a8ac28 100644
--- a/src/frontend/A32/translate/translate_arm/exception_generating.cpp
+++ b/src/frontend/A32/translate/translate_arm/exception_generating.cpp
@@ -10,33 +10,37 @@
 
 namespace Dynarmic::A32 {
 
+// BKPT #<imm16>
 bool ArmTranslatorVisitor::arm_BKPT(Cond cond, Imm12 /*imm12*/, Imm4 /*imm4*/) {
     if (cond != Cond::AL && !options.define_unpredictable_behaviour) {
         return UnpredictableInstruction();
     }
     // UNPREDICTABLE: The instruction executes conditionally.
 
-    if (ConditionPassed(cond)) {
-        ir.ExceptionRaised(Exception::Breakpoint);
-        ir.SetTerm(IR::Term::CheckHalt{IR::Term::ReturnToDispatch{}});
-        return false;
+    if (!ConditionPassed(cond)) {
+        return true;
     }
-    return true;
+
+    ir.ExceptionRaised(Exception::Breakpoint);
+    ir.SetTerm(IR::Term::CheckHalt{IR::Term::ReturnToDispatch{}});
+    return false;
 }
 
+// SVC<c> #<imm24>
 bool ArmTranslatorVisitor::arm_SVC(Cond cond, Imm24 imm24) {
-    u32 imm32 = imm24;
-    // SVC<c> #<imm24>
-    if (ConditionPassed(cond)) {
-        ir.PushRSB(ir.current_location.AdvancePC(4));
-        ir.BranchWritePC(ir.Imm32(ir.current_location.PC() + 4));
-        ir.CallSupervisor(ir.Imm32(imm32));
-        ir.SetTerm(IR::Term::CheckHalt{IR::Term::PopRSBHint{}});
-        return false;
+    if (!ConditionPassed(cond)) {
+        return true;
     }
-    return true;
+
+    const u32 imm32 = imm24;
+    ir.PushRSB(ir.current_location.AdvancePC(4));
+    ir.BranchWritePC(ir.Imm32(ir.current_location.PC() + 4));
+    ir.CallSupervisor(ir.Imm32(imm32));
+    ir.SetTerm(IR::Term::CheckHalt{IR::Term::PopRSBHint{}});
+    return false;
 }
 
+// UDF<c> #<imm16>
 bool ArmTranslatorVisitor::arm_UDF() {
     return UndefinedInstruction();
 }