From c3a3b9687e3f7b781f834bd310cefb85750f122b Mon Sep 17 00:00:00 2001 From: Lioncash Date: Mon, 17 Sep 2018 21:15:59 -0400 Subject: [PATCH] data_processing_logical: Move datasize declarations after early-exit conditionals While we're at it, make variables const where applicable. --- .../impl/data_processing_logical.cpp | 177 ++++++++++-------- 1 file changed, 100 insertions(+), 77 deletions(-) diff --git a/src/frontend/A64/translate/impl/data_processing_logical.cpp b/src/frontend/A64/translate/impl/data_processing_logical.cpp index 9bf44e37..c22c6cc4 100644 --- a/src/frontend/A64/translate/impl/data_processing_logical.cpp +++ b/src/frontend/A64/translate/impl/data_processing_logical.cpp @@ -9,8 +9,10 @@ namespace Dynarmic::A64 { bool TranslatorVisitor::AND_imm(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg Rn, Reg Rd) { - size_t datasize = sf ? 64 : 32; - if (!sf && N) return ReservedValue(); + if (!sf && N) { + return ReservedValue(); + } + u64 imm; if (auto masks = DecodeBitMasks(N, imms, immr, true)) { imm = masks->wmask; @@ -18,9 +20,10 @@ bool TranslatorVisitor::AND_imm(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg R return ReservedValue(); } - auto operand1 = X(datasize, Rn); + const size_t datasize = sf ? 64 : 32; + const auto operand1 = X(datasize, Rn); - auto result = ir.And(operand1, I(datasize, imm)); + const auto result = ir.And(operand1, I(datasize, imm)); if (Rd == Reg::SP) { SP(datasize, result); } else { @@ -31,8 +34,10 @@ bool TranslatorVisitor::AND_imm(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg R } bool TranslatorVisitor::ORR_imm(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg Rn, Reg Rd) { - size_t datasize = sf ? 64 : 32; - if (!sf && N) return ReservedValue(); + if (!sf && N) { + return ReservedValue(); + } + u64 imm; if (auto masks = DecodeBitMasks(N, imms, immr, true)) { imm = masks->wmask; @@ -40,9 +45,10 @@ bool TranslatorVisitor::ORR_imm(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg R return ReservedValue(); } - auto operand1 = X(datasize, Rn); + const size_t datasize = sf ? 64 : 32; + const auto operand1 = X(datasize, Rn); - auto result = ir.Or(operand1, I(datasize, imm)); + const auto result = ir.Or(operand1, I(datasize, imm)); if (Rd == Reg::SP) { SP(datasize, result); } else { @@ -53,8 +59,10 @@ bool TranslatorVisitor::ORR_imm(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg R } bool TranslatorVisitor::EOR_imm(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg Rn, Reg Rd) { - size_t datasize = sf ? 64 : 32; - if (!sf && N) return ReservedValue(); + if (!sf && N) { + return ReservedValue(); + } + u64 imm; if (auto masks = DecodeBitMasks(N, imms, immr, true)) { imm = masks->wmask; @@ -62,9 +70,10 @@ bool TranslatorVisitor::EOR_imm(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg R return ReservedValue(); } - auto operand1 = X(datasize, Rn); + const size_t datasize = sf ? 64 : 32; + const auto operand1 = X(datasize, Rn); - auto result = ir.Eor(operand1, I(datasize, imm)); + const auto result = ir.Eor(operand1, I(datasize, imm)); if (Rd == Reg::SP) { SP(datasize, result); } else { @@ -75,8 +84,10 @@ bool TranslatorVisitor::EOR_imm(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg R } bool TranslatorVisitor::ANDS_imm(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg Rn, Reg Rd) { - size_t datasize = sf ? 64 : 32; - if (!sf && N) return ReservedValue(); + if (!sf && N) { + return ReservedValue(); + } + u64 imm; if (auto masks = DecodeBitMasks(N, imms, immr, true)) { imm = masks->wmask; @@ -84,130 +95,142 @@ bool TranslatorVisitor::ANDS_imm(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg return ReservedValue(); } - auto operand1 = X(datasize, Rn); + const size_t datasize = sf ? 64 : 32; + const auto operand1 = X(datasize, Rn); + const auto result = ir.And(operand1, I(datasize, imm)); - auto result = ir.And(operand1, I(datasize, imm)); ir.SetNZCV(ir.NZCVFrom(result)); X(datasize, Rd, result); - return true; } bool TranslatorVisitor::AND_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd) { - size_t datasize = sf ? 64 : 32; - if (!sf && imm6.Bit<5>()) return ReservedValue(); - u8 shift_amount = imm6.ZeroExtend(); + if (!sf && imm6.Bit<5>()) { + return ReservedValue(); + } - auto operand1 = X(datasize, Rn); - auto operand2 = ShiftReg(datasize, Rm, shift, ir.Imm8(shift_amount)); + const size_t datasize = sf ? 64 : 32; + const u8 shift_amount = imm6.ZeroExtend(); + + const auto operand1 = X(datasize, Rn); + const auto operand2 = ShiftReg(datasize, Rm, shift, ir.Imm8(shift_amount)); + const auto result = ir.And(operand1, operand2); - auto result = ir.And(operand1, operand2); X(datasize, Rd, result); - return true; } bool TranslatorVisitor::BIC_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd) { - size_t datasize = sf ? 64 : 32; - if (!sf && imm6.Bit<5>()) return ReservedValue(); - u8 shift_amount = imm6.ZeroExtend(); + if (!sf && imm6.Bit<5>()) { + return ReservedValue(); + } - auto operand1 = X(datasize, Rn); - auto operand2 = ShiftReg(datasize, Rm, shift, ir.Imm8(shift_amount)); + const size_t datasize = sf ? 64 : 32; + const u8 shift_amount = imm6.ZeroExtend(); + + const auto operand1 = X(datasize, Rn); + const auto operand2 = ir.Not(ShiftReg(datasize, Rm, shift, ir.Imm8(shift_amount))); + const auto result = ir.And(operand1, operand2); - operand2 = ir.Not(operand2); - auto result = ir.And(operand1, operand2); X(datasize, Rd, result); - return true; } bool TranslatorVisitor::ORR_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd) { - size_t datasize = sf ? 64 : 32; - if (!sf && imm6.Bit<5>()) return ReservedValue(); - u8 shift_amount = imm6.ZeroExtend(); + if (!sf && imm6.Bit<5>()) { + return ReservedValue(); + } - auto operand1 = X(datasize, Rn); - auto operand2 = ShiftReg(datasize, Rm, shift, ir.Imm8(shift_amount)); + const size_t datasize = sf ? 64 : 32; + const u8 shift_amount = imm6.ZeroExtend(); + + const auto operand1 = X(datasize, Rn); + const auto operand2 = ShiftReg(datasize, Rm, shift, ir.Imm8(shift_amount)); + const auto result = ir.Or(operand1, operand2); - auto result = ir.Or(operand1, operand2); X(datasize, Rd, result); - return true; } bool TranslatorVisitor::ORN_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd) { - size_t datasize = sf ? 64 : 32; - if (!sf && imm6.Bit<5>()) return ReservedValue(); - u8 shift_amount = imm6.ZeroExtend(); + if (!sf && imm6.Bit<5>()) { + return ReservedValue(); + } - auto operand1 = X(datasize, Rn); - auto operand2 = ShiftReg(datasize, Rm, shift, ir.Imm8(shift_amount)); + const size_t datasize = sf ? 64 : 32; + const u8 shift_amount = imm6.ZeroExtend(); + + const auto operand1 = X(datasize, Rn); + const auto operand2 = ir.Not(ShiftReg(datasize, Rm, shift, ir.Imm8(shift_amount))); + const auto result = ir.Or(operand1, operand2); - operand2 = ir.Not(operand2); - auto result = ir.Or(operand1, operand2); X(datasize, Rd, result); - return true; } bool TranslatorVisitor::EOR_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd) { - size_t datasize = sf ? 64 : 32; - if (!sf && imm6.Bit<5>()) return ReservedValue(); - u8 shift_amount = imm6.ZeroExtend(); + if (!sf && imm6.Bit<5>()) { + return ReservedValue(); + } - auto operand1 = X(datasize, Rn); - auto operand2 = ShiftReg(datasize, Rm, shift, ir.Imm8(shift_amount)); + const size_t datasize = sf ? 64 : 32; + const u8 shift_amount = imm6.ZeroExtend(); + + const auto operand1 = X(datasize, Rn); + const auto operand2 = ShiftReg(datasize, Rm, shift, ir.Imm8(shift_amount)); + const auto result = ir.Eor(operand1, operand2); - auto result = ir.Eor(operand1, operand2); X(datasize, Rd, result); - return true; } bool TranslatorVisitor::EON(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd) { - size_t datasize = sf ? 64 : 32; - if (!sf && imm6.Bit<5>()) return ReservedValue(); - u8 shift_amount = imm6.ZeroExtend(); + if (!sf && imm6.Bit<5>()) { + return ReservedValue(); + } - auto operand1 = X(datasize, Rn); - auto operand2 = ShiftReg(datasize, Rm, shift, ir.Imm8(shift_amount)); + const size_t datasize = sf ? 64 : 32; + const u8 shift_amount = imm6.ZeroExtend(); + + const auto operand1 = X(datasize, Rn); + const auto operand2 = ir.Not(ShiftReg(datasize, Rm, shift, ir.Imm8(shift_amount))); + const auto result = ir.Eor(operand1, operand2); - operand2 = ir.Not(operand2); - auto result = ir.Eor(operand1, operand2); X(datasize, Rd, result); - return true; } bool TranslatorVisitor::ANDS_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd) { - size_t datasize = sf ? 64 : 32; - if (!sf && imm6.Bit<5>()) return ReservedValue(); - u8 shift_amount = imm6.ZeroExtend(); + if (!sf && imm6.Bit<5>()) { + return ReservedValue(); + } - auto operand1 = X(datasize, Rn); - auto operand2 = ShiftReg(datasize, Rm, shift, ir.Imm8(shift_amount)); + const size_t datasize = sf ? 64 : 32; + const u8 shift_amount = imm6.ZeroExtend(); + + const auto operand1 = X(datasize, Rn); + const auto operand2 = ShiftReg(datasize, Rm, shift, ir.Imm8(shift_amount)); + const auto result = ir.And(operand1, operand2); - auto result = ir.And(operand1, operand2); ir.SetNZCV(ir.NZCVFrom(result)); X(datasize, Rd, result); - return true; } bool TranslatorVisitor::BICS(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd) { - size_t datasize = sf ? 64 : 32; - if (!sf && imm6.Bit<5>()) return ReservedValue(); - u8 shift_amount = imm6.ZeroExtend(); + if (!sf && imm6.Bit<5>()) { + return ReservedValue(); + } - auto operand1 = X(datasize, Rn); - auto operand2 = ShiftReg(datasize, Rm, shift, ir.Imm8(shift_amount)); + const size_t datasize = sf ? 64 : 32; + const u8 shift_amount = imm6.ZeroExtend(); + + const auto operand1 = X(datasize, Rn); + const auto operand2 = ir.Not(ShiftReg(datasize, Rm, shift, ir.Imm8(shift_amount))); + const auto result = ir.And(operand1, operand2); - operand2 = ir.Not(operand2); - auto result = ir.And(operand1, operand2); ir.SetNZCV(ir.NZCVFrom(result)); X(datasize, Rd, result); - return true; }