From c7785cd9820a04466d2ff687f52b7e2796e3a2dc Mon Sep 17 00:00:00 2001 From: MerryMage Date: Sun, 21 Jun 2020 12:04:03 +0100 Subject: [PATCH] A32: Implement ASIMD VUZP and VZIP --- src/frontend/A32/decoder/asimd.inc | 4 +- .../translate/impl/asimd_two_regs_misc.cpp | 67 +++++++++++++++++++ .../A32/translate/impl/translate_arm.h | 2 + 3 files changed, 71 insertions(+), 2 deletions(-) diff --git a/src/frontend/A32/decoder/asimd.inc b/src/frontend/A32/decoder/asimd.inc index 2daf856c..13f8f117 100644 --- a/src/frontend/A32/decoder/asimd.inc +++ b/src/frontend/A32/decoder/asimd.inc @@ -100,8 +100,8 @@ INST(asimd_VABS, "VABS", "111100111D11zz01dddd0F1 INST(asimd_VNEG, "VNEG", "111100111D11zz01dddd0F111QM0mmmm") // ASIMD INST(asimd_VSWP, "VSWP", "111100111D110010dddd00000QM0mmmm") // ASIMD INST(asimd_VTRN, "VTRN", "111100111D11zz10dddd00001QM0mmmm") // ASIMD -//INST(asimd_VUZP, "VUZP", "111100111-11--10----00010x-0----") // ASIMD -//INST(asimd_VZIP, "VZIP", "111100111-11--10----00011x-0----") // ASIMD +INST(asimd_VUZP, "VUZP", "111100111D11zz10dddd00010QM0mmmm") // ASIMD +INST(asimd_VZIP, "VZIP", "111100111D11zz10dddd00011QM0mmmm") // ASIMD //INST(asimd_VMOVN, "VMOVN", "111100111-11--10----001000-0----") // ASIMD //INST(asimd_VQMOVUN, "VQMOVUN", "111100111-11--10----001001-0----") // ASIMD //INST(asimd_VQMOVN, "VQMOVN", "111100111-11--10----00101x-0----") // ASIMD diff --git a/src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp b/src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp index c9c08e4c..24225a60 100644 --- a/src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp +++ b/src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp @@ -424,6 +424,73 @@ bool ArmTranslatorVisitor::asimd_VTRN(bool D, size_t sz, size_t Vd, bool Q, bool return true; } +bool ArmTranslatorVisitor::asimd_VUZP(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm) { + if (sz == 0b11 || (!Q && sz == 0b10)) { + return UndefinedInstruction(); + } + + if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) { + return UndefinedInstruction(); + } + + const size_t esize = 8U << sz; + const auto d = ToVector(Q, Vd, D); + const auto m = ToVector(Q, Vm, M); + + if (d == m) { + return UnpredictableInstruction(); + } + + const auto reg_d = ir.GetVector(d); + const auto reg_m = ir.GetVector(m); + auto result_d = ir.VectorDeinterleaveEven(esize, reg_d, reg_m); + auto result_m = ir.VectorDeinterleaveOdd(esize, reg_d, reg_m); + + if (!Q) { + result_d = ir.VectorShuffleWords(result_d, 0b11011000); + result_m = ir.VectorShuffleWords(result_m, 0b11011000); + } + + ir.SetVector(d, result_d); + ir.SetVector(m, result_m); + return true; +} + +bool ArmTranslatorVisitor::asimd_VZIP(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm) { + if (sz == 0b11 || (!Q && sz == 0b10)) { + return UndefinedInstruction(); + } + + if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) { + return UndefinedInstruction(); + } + + const size_t esize = 8U << sz; + const auto d = ToVector(Q, Vd, D); + const auto m = ToVector(Q, Vm, M); + + if (d == m) { + return UnpredictableInstruction(); + } + + const auto reg_d = ir.GetVector(d); + const auto reg_m = ir.GetVector(m); + + if (Q){ + const auto result_d = ir.VectorInterleaveLower(esize, reg_d, reg_m); + const auto result_m = ir.VectorInterleaveUpper(esize, reg_d, reg_m); + + ir.SetVector(d, result_d); + ir.SetVector(m, result_m); + } else { + const auto result = ir.VectorInterleaveLower(esize, reg_d, reg_m); + + ir.SetExtendedRegister(d, ir.VectorGetElement(64, result, 0)); + ir.SetExtendedRegister(m, ir.VectorGetElement(64, result, 1)); + } + return true; +} + bool ArmTranslatorVisitor::asimd_VRECPE(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm) { if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) { return UndefinedInstruction(); diff --git a/src/frontend/A32/translate/impl/translate_arm.h b/src/frontend/A32/translate/impl/translate_arm.h index 83f88ca9..6ad84db6 100644 --- a/src/frontend/A32/translate/impl/translate_arm.h +++ b/src/frontend/A32/translate/impl/translate_arm.h @@ -528,6 +528,8 @@ struct ArmTranslatorVisitor final { bool asimd_VNEG(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm); bool asimd_VSWP(bool D, size_t Vd, bool Q, bool M, size_t Vm); bool asimd_VTRN(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm); + bool asimd_VUZP(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm); + bool asimd_VZIP(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm); bool asimd_VRECPE(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm); bool asimd_VRSQRTE(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm);