From c82fa5ec5a34950def349ba8da8258d586aa56a6 Mon Sep 17 00:00:00 2001 From: Lioncash Date: Mon, 17 Sep 2018 21:05:32 -0400 Subject: [PATCH] data_processing_addsub: Move datasize declarations after early-exit conditionals While we're at it, also make relevant variables const where applicable --- .../translate/impl/data_processing_addsub.cpp | 200 +++++++++--------- 1 file changed, 104 insertions(+), 96 deletions(-) diff --git a/src/frontend/A64/translate/impl/data_processing_addsub.cpp b/src/frontend/A64/translate/impl/data_processing_addsub.cpp index 87771017..7f7013af 100644 --- a/src/frontend/A64/translate/impl/data_processing_addsub.cpp +++ b/src/frontend/A64/translate/impl/data_processing_addsub.cpp @@ -9,8 +9,6 @@ namespace Dynarmic::A64 { bool TranslatorVisitor::ADD_imm(bool sf, Imm<2> shift, Imm<12> imm12, Reg Rn, Reg Rd) { - size_t datasize = sf ? 64 : 32; - u64 imm; switch (shift.ZeroExtend()) { case 0b00: @@ -23,9 +21,10 @@ bool TranslatorVisitor::ADD_imm(bool sf, Imm<2> shift, Imm<12> imm12, Reg Rn, Re return ReservedValue(); } - auto operand1 = Rn == Reg::SP ? SP(datasize) : IR::U32U64(X(datasize, Rn)); + const size_t datasize = sf ? 64 : 32; + const auto operand1 = Rn == Reg::SP ? SP(datasize) : IR::U32U64(X(datasize, Rn)); - auto result = ir.Add(operand1, I(datasize, imm)); + const auto result = ir.Add(operand1, I(datasize, imm)); if (Rd == Reg::SP) { SP(datasize, result); @@ -37,8 +36,6 @@ bool TranslatorVisitor::ADD_imm(bool sf, Imm<2> shift, Imm<12> imm12, Reg Rn, Re } bool TranslatorVisitor::ADDS_imm(bool sf, Imm<2> shift, Imm<12> imm12, Reg Rn, Reg Rd) { - size_t datasize = sf ? 64 : 32; - u64 imm; switch (shift.ZeroExtend()) { case 0b00: @@ -51,20 +48,18 @@ bool TranslatorVisitor::ADDS_imm(bool sf, Imm<2> shift, Imm<12> imm12, Reg Rn, R return ReservedValue(); } - auto operand1 = Rn == Reg::SP ? SP(datasize) : IR::U32U64(X(datasize, Rn)); + const size_t datasize = sf ? 64 : 32; + const auto operand1 = Rn == Reg::SP ? SP(datasize) : IR::U32U64(X(datasize, Rn)); - auto result = ir.Add(operand1, I(datasize, imm)); + const auto result = ir.Add(operand1, I(datasize, imm)); ir.SetNZCV(ir.NZCVFrom(result)); X(datasize, Rd, result); - return true; } bool TranslatorVisitor::SUB_imm(bool sf, Imm<2> shift, Imm<12> imm12, Reg Rn, Reg Rd) { - size_t datasize = sf ? 64 : 32; - u64 imm; switch (shift.ZeroExtend()) { case 0b00: @@ -77,9 +72,10 @@ bool TranslatorVisitor::SUB_imm(bool sf, Imm<2> shift, Imm<12> imm12, Reg Rn, Re return ReservedValue(); } - auto operand1 = Rn == Reg::SP ? SP(datasize) : IR::U32U64(X(datasize, Rn)); + const size_t datasize = sf ? 64 : 32; + const auto operand1 = Rn == Reg::SP ? SP(datasize) : IR::U32U64(X(datasize, Rn)); - auto result = ir.Sub(operand1, I(datasize, imm)); + const auto result = ir.Sub(operand1, I(datasize, imm)); if (Rd == Reg::SP) { SP(datasize, result); @@ -91,8 +87,6 @@ bool TranslatorVisitor::SUB_imm(bool sf, Imm<2> shift, Imm<12> imm12, Reg Rn, Re } bool TranslatorVisitor::SUBS_imm(bool sf, Imm<2> shift, Imm<12> imm12, Reg Rn, Reg Rd) { - size_t datasize = sf ? 64 : 32; - u64 imm; switch (shift.ZeroExtend()) { case 0b00: @@ -105,102 +99,116 @@ bool TranslatorVisitor::SUBS_imm(bool sf, Imm<2> shift, Imm<12> imm12, Reg Rn, R return ReservedValue(); } - auto operand1 = Rn == Reg::SP ? SP(datasize) : IR::U32U64(X(datasize, Rn)); + const size_t datasize = sf ? 64 : 32; + const auto operand1 = Rn == Reg::SP ? SP(datasize) : IR::U32U64(X(datasize, Rn)); - auto result = ir.Sub(operand1, I(datasize, imm)); + const auto result = ir.Sub(operand1, I(datasize, imm)); ir.SetNZCV(ir.NZCVFrom(result)); X(datasize, Rd, result); - return true; } bool TranslatorVisitor::ADD_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd) { - size_t datasize = sf ? 64 : 32; + if (shift == 0b11) { + return ReservedValue(); + } - if (shift == 0b11) return ReservedValue(); - if (!sf && imm6.Bit<5>()) return ReservedValue(); + if (!sf && imm6.Bit<5>()) { + return ReservedValue(); + } - u8 shift_amount = imm6.ZeroExtend(); + const size_t datasize = sf ? 64 : 32; + const u8 shift_amount = imm6.ZeroExtend(); - auto operand1 = X(datasize, Rn); - auto operand2 = ShiftReg(datasize, Rm, shift, ir.Imm8(shift_amount)); + const auto operand1 = X(datasize, Rn); + const auto operand2 = ShiftReg(datasize, Rm, shift, ir.Imm8(shift_amount)); - auto result = ir.Add(operand1, operand2); + const auto result = ir.Add(operand1, operand2); X(datasize, Rd, result); - return true; } bool TranslatorVisitor::ADDS_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd) { - size_t datasize = sf ? 64 : 32; + if (shift == 0b11) { + return ReservedValue(); + } - if (shift == 0b11) return ReservedValue(); - if (!sf && imm6.Bit<5>()) return ReservedValue(); + if (!sf && imm6.Bit<5>()) { + return ReservedValue(); + } - u8 shift_amount = imm6.ZeroExtend(); + const size_t datasize = sf ? 64 : 32; + const u8 shift_amount = imm6.ZeroExtend(); - auto operand1 = X(datasize, Rn); - auto operand2 = ShiftReg(datasize, Rm, shift, ir.Imm8(shift_amount)); + const auto operand1 = X(datasize, Rn); + const auto operand2 = ShiftReg(datasize, Rm, shift, ir.Imm8(shift_amount)); - auto result = ir.Add(operand1, operand2); + const auto result = ir.Add(operand1, operand2); ir.SetNZCV(ir.NZCVFrom(result)); X(datasize, Rd, result); - return true; } bool TranslatorVisitor::SUB_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd) { - size_t datasize = sf ? 64 : 32; + if (shift == 0b11) { + return ReservedValue(); + } - if (shift == 0b11) return ReservedValue(); - if (!sf && imm6.Bit<5>()) return ReservedValue(); + if (!sf && imm6.Bit<5>()) { + return ReservedValue(); + } - u8 shift_amount = imm6.ZeroExtend(); + const size_t datasize = sf ? 64 : 32; + const u8 shift_amount = imm6.ZeroExtend(); - auto operand1 = X(datasize, Rn); - auto operand2 = ShiftReg(datasize, Rm, shift, ir.Imm8(shift_amount)); + const auto operand1 = X(datasize, Rn); + const auto operand2 = ShiftReg(datasize, Rm, shift, ir.Imm8(shift_amount)); - auto result = ir.Sub(operand1, operand2); + const auto result = ir.Sub(operand1, operand2); X(datasize, Rd, result); - return true; } bool TranslatorVisitor::SUBS_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd) { - size_t datasize = sf ? 64 : 32; + if (shift == 0b11) { + return ReservedValue(); + } - if (shift == 0b11) return ReservedValue(); - if (!sf && imm6.Bit<5>()) return ReservedValue(); + if (!sf && imm6.Bit<5>()) { + return ReservedValue(); + } - u8 shift_amount = imm6.ZeroExtend(); + const size_t datasize = sf ? 64 : 32; + const u8 shift_amount = imm6.ZeroExtend(); - auto operand1 = X(datasize, Rn); - auto operand2 = ShiftReg(datasize, Rm, shift, ir.Imm8(shift_amount)); + const auto operand1 = X(datasize, Rn); + const auto operand2 = ShiftReg(datasize, Rm, shift, ir.Imm8(shift_amount)); - auto result = ir.Sub(operand1, operand2); + const auto result = ir.Sub(operand1, operand2); ir.SetNZCV(ir.NZCVFrom(result)); X(datasize, Rd, result); - return true; } bool TranslatorVisitor::ADD_ext(bool sf, Reg Rm, Imm<3> option, Imm<3> imm3, Reg Rn, Reg Rd) { - size_t datasize = sf ? 64 : 32; - u8 shift = imm3.ZeroExtend(); - if (shift > 4) return ReservedValue(); + const u8 shift = imm3.ZeroExtend(); + if (shift > 4) { + return ReservedValue(); + } - auto operand1 = Rn == Reg::SP ? SP(datasize) : IR::U32U64(X(datasize, Rn)); - auto operand2 = ExtendReg(datasize, Rm, option, shift); + const size_t datasize = sf ? 64 : 32; + const auto operand1 = Rn == Reg::SP ? SP(datasize) : IR::U32U64(X(datasize, Rn)); + const auto operand2 = ExtendReg(datasize, Rm, option, shift); - auto result = ir.Add(operand1, operand2); + const auto result = ir.Add(operand1, operand2); if (Rd == Reg::SP) { SP(datasize, result); @@ -212,31 +220,34 @@ bool TranslatorVisitor::ADD_ext(bool sf, Reg Rm, Imm<3> option, Imm<3> imm3, Reg } bool TranslatorVisitor::ADDS_ext(bool sf, Reg Rm, Imm<3> option, Imm<3> imm3, Reg Rn, Reg Rd) { - size_t datasize = sf ? 64 : 32; - u8 shift = imm3.ZeroExtend(); - if (shift > 4) return ReservedValue(); + const u8 shift = imm3.ZeroExtend(); + if (shift > 4) { + return ReservedValue(); + } - auto operand1 = Rn == Reg::SP ? SP(datasize) : IR::U32U64(X(datasize, Rn)); - auto operand2 = ExtendReg(datasize, Rm, option, shift); + const size_t datasize = sf ? 64 : 32; + const auto operand1 = Rn == Reg::SP ? SP(datasize) : IR::U32U64(X(datasize, Rn)); + const auto operand2 = ExtendReg(datasize, Rm, option, shift); - auto result = ir.Add(operand1, operand2); + const auto result = ir.Add(operand1, operand2); ir.SetNZCV(ir.NZCVFrom(result)); X(datasize, Rd, result); - return true; } bool TranslatorVisitor::SUB_ext(bool sf, Reg Rm, Imm<3> option, Imm<3> imm3, Reg Rn, Reg Rd) { - size_t datasize = sf ? 64 : 32; - u8 shift = imm3.ZeroExtend(); - if (shift > 4) return ReservedValue(); + const u8 shift = imm3.ZeroExtend(); + if (shift > 4) { + return ReservedValue(); + } - auto operand1 = Rn == Reg::SP ? SP(datasize) : IR::U32U64(X(datasize, Rn)); - auto operand2 = ExtendReg(datasize, Rm, option, shift); + const size_t datasize = sf ? 64 : 32; + const auto operand1 = Rn == Reg::SP ? SP(datasize) : IR::U32U64(X(datasize, Rn)); + const auto operand2 = ExtendReg(datasize, Rm, option, shift); - auto result = ir.Sub(operand1, operand2); + const auto result = ir.Sub(operand1, operand2); if (Rd == Reg::SP) { SP(datasize, result); @@ -248,75 +259,72 @@ bool TranslatorVisitor::SUB_ext(bool sf, Reg Rm, Imm<3> option, Imm<3> imm3, Reg } bool TranslatorVisitor::SUBS_ext(bool sf, Reg Rm, Imm<3> option, Imm<3> imm3, Reg Rn, Reg Rd) { - size_t datasize = sf ? 64 : 32; - u8 shift = imm3.ZeroExtend(); - if (shift > 4) return ReservedValue(); + const u8 shift = imm3.ZeroExtend(); + if (shift > 4) { + return ReservedValue(); + } - auto operand1 = Rn == Reg::SP ? SP(datasize) : IR::U32U64(X(datasize, Rn)); - auto operand2 = ExtendReg(datasize, Rm, option, shift); + const size_t datasize = sf ? 64 : 32; + const auto operand1 = Rn == Reg::SP ? SP(datasize) : IR::U32U64(X(datasize, Rn)); + const auto operand2 = ExtendReg(datasize, Rm, option, shift); - auto result = ir.Sub(operand1, operand2); + const auto result = ir.Sub(operand1, operand2); ir.SetNZCV(ir.NZCVFrom(result)); X(datasize, Rd, result); - return true; } bool TranslatorVisitor::ADC(bool sf, Reg Rm, Reg Rn, Reg Rd) { - size_t datasize = sf ? 64 : 32; + const size_t datasize = sf ? 64 : 32; - IR::U32U64 operand1 = X(datasize, Rn); - IR::U32U64 operand2 = X(datasize, Rm); + const IR::U32U64 operand1 = X(datasize, Rn); + const IR::U32U64 operand2 = X(datasize, Rm); - auto result = ir.AddWithCarry(operand1, operand2, ir.GetCFlag()); + const auto result = ir.AddWithCarry(operand1, operand2, ir.GetCFlag()); X(datasize, Rd, result); - return true; } bool TranslatorVisitor::ADCS(bool sf, Reg Rm, Reg Rn, Reg Rd) { - size_t datasize = sf ? 64 : 32; + const size_t datasize = sf ? 64 : 32; - IR::U32U64 operand1 = X(datasize, Rn); - IR::U32U64 operand2 = X(datasize, Rm); + const IR::U32U64 operand1 = X(datasize, Rn); + const IR::U32U64 operand2 = X(datasize, Rm); - auto result = ir.AddWithCarry(operand1, operand2, ir.GetCFlag()); + const auto result = ir.AddWithCarry(operand1, operand2, ir.GetCFlag()); ir.SetNZCV(ir.NZCVFrom(result)); X(datasize, Rd, result); - return true; } bool TranslatorVisitor::SBC(bool sf, Reg Rm, Reg Rn, Reg Rd) { - size_t datasize = sf ? 64 : 32; + const size_t datasize = sf ? 64 : 32; - IR::U32U64 operand1 = X(datasize, Rn); - IR::U32U64 operand2 = X(datasize, Rm); + const IR::U32U64 operand1 = X(datasize, Rn); + const IR::U32U64 operand2 = X(datasize, Rm); - auto result = ir.SubWithCarry(operand1, operand2, ir.GetCFlag()); + const auto result = ir.SubWithCarry(operand1, operand2, ir.GetCFlag()); X(datasize, Rd, result); - return true; } bool TranslatorVisitor::SBCS(bool sf, Reg Rm, Reg Rn, Reg Rd) { - size_t datasize = sf ? 64 : 32; + const size_t datasize = sf ? 64 : 32; - IR::U32U64 operand1 = X(datasize, Rn); - IR::U32U64 operand2 = X(datasize, Rm); + const IR::U32U64 operand1 = X(datasize, Rn); + const IR::U32U64 operand2 = X(datasize, Rm); - auto result = ir.SubWithCarry(operand1, operand2, ir.GetCFlag()); + const auto result = ir.SubWithCarry(operand1, operand2, ir.GetCFlag()); ir.SetNZCV(ir.NZCVFrom(result)); X(datasize, Rd, result); - return true; }