From cc9efd13c90ccedc09dd943fcd4aed91837de765 Mon Sep 17 00:00:00 2001 From: MerryMage Date: Mon, 5 Feb 2018 15:41:41 +0000 Subject: [PATCH] A64: Implement STLLRB, STLLRH, STLLR, LDLARB, LDLARH, LDLAR --- src/frontend/A64/decoder/a64.inc | 4 ++-- .../A64/translate/impl/load_store_exclusive.cpp | 14 ++++++++++++++ tests/A64/fuzz_with_unicorn.cpp | 15 ++++++++++++++- 3 files changed, 30 insertions(+), 3 deletions(-) diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc index 8bca9482..5fdc85bd 100644 --- a/src/frontend/A64/decoder/a64.inc +++ b/src/frontend/A64/decoder/a64.inc @@ -132,9 +132,9 @@ INST(LDx_mult_2, "LDx (multiple structures)", "0Q001 //INST(LDAXRB, "LDAXRB", "zz00100001011111111111nnnnnttttt") //INST(LDXP, "LDXP", "1z001000011111110uuuuunnnnnttttt") //INST(LDAXP, "LDAXP", "1z001000011111111uuuuunnnnnttttt") -//INST(STLLR, "STLLRB, STLLRH, STLLR", "zz00100010011111011111nnnnnttttt") +INST(STLLR, "STLLRB, STLLRH, STLLR", "zz00100010011111011111nnnnnttttt") INST(STLR, "STLRB, STLRH, STLR", "zz00100010011111111111nnnnnttttt") -//INST(LDLAR, "LDLARB, LDLARH, LDLAR", "zz00100011011111011111nnnnnttttt") +INST(LDLAR, "LDLARB, LDLARH, LDLAR", "zz00100011011111011111nnnnnttttt") INST(LDAR, "LDARB, LDARH, LDAR", "zz00100011011111111111nnnnnttttt") //INST(CASP, "CASP, CASPA, CASPAL, CASPL", "0z0010000L1sssssp11111nnnnnttttt") // ARMv8.1 //INST(CASB, "CASB, CASAB, CASALB, CASLB", "000010001L1sssssp11111nnnnnttttt") // ARMv8.1 diff --git a/src/frontend/A64/translate/impl/load_store_exclusive.cpp b/src/frontend/A64/translate/impl/load_store_exclusive.cpp index e5bb3705..70129ebf 100644 --- a/src/frontend/A64/translate/impl/load_store_exclusive.cpp +++ b/src/frontend/A64/translate/impl/load_store_exclusive.cpp @@ -47,6 +47,13 @@ static bool OrderedSharedDecodeAndOperation(TranslatorVisitor& tv, size_t size, return true; } +bool TranslatorVisitor::STLLR(Imm<2> sz, Reg Rn, Reg Rt) { + const size_t size = sz.ZeroExtend(); + const bool L = 0; + const bool o0 = 0; + return OrderedSharedDecodeAndOperation(*this, size, L, o0, Rn, Rt); +} + bool TranslatorVisitor::STLR(Imm<2> sz, Reg Rn, Reg Rt) { const size_t size = sz.ZeroExtend(); const bool L = 0; @@ -54,6 +61,13 @@ bool TranslatorVisitor::STLR(Imm<2> sz, Reg Rn, Reg Rt) { return OrderedSharedDecodeAndOperation(*this, size, L, o0, Rn, Rt); } +bool TranslatorVisitor::LDLAR(Imm<2> sz, Reg Rn, Reg Rt) { + const size_t size = sz.ZeroExtend(); + const bool L = 1; + const bool o0 = 0; + return OrderedSharedDecodeAndOperation(*this, size, L, o0, Rn, Rt); +} + bool TranslatorVisitor::LDAR(Imm<2> sz, Reg Rn, Reg Rt) { const size_t size = sz.ZeroExtend(); const bool L = 1; diff --git a/tests/A64/fuzz_with_unicorn.cpp b/tests/A64/fuzz_with_unicorn.cpp index 15157351..509f4ade 100644 --- a/tests/A64/fuzz_with_unicorn.cpp +++ b/tests/A64/fuzz_with_unicorn.cpp @@ -4,7 +4,10 @@ * General Public License version 2 or any later version. */ +#include #include +#include +#include #include @@ -41,8 +44,18 @@ static u32 GenRandomInst(u64 pc, bool is_last_inst) { std::vector result; + // List of instructions not to test + const std::vector do_not_test { + // Unallocated encodings are invalid. + "UnallocatedEncoding", + // Unimplemented in QEMU + "STLLR", + // Unimplemented in QEMU + "LDLAR", + }; + for (const auto& [fn, bitstring] : list) { - if (std::strcmp(fn, "UnallocatedEncoding") == 0) { + if (std::find(do_not_test.begin(), do_not_test.end(), fn) != do_not_test.end()) { InstructionGenerator::AddInvalidInstruction(bitstring); continue; }