From cd537dc7115118cec701a5611e6622d595cf6c12 Mon Sep 17 00:00:00 2001 From: Merry Date: Sat, 30 Jul 2022 12:24:17 +0100 Subject: [PATCH] IR: Rename PackedAbsDiffSumS8 to PackedAbsDiffSumU8 --- src/dynarmic/backend/arm64/emit_arm64_packed.cpp | 4 ++-- src/dynarmic/backend/x64/emit_x64_packed.cpp | 2 +- src/dynarmic/frontend/A32/translate/impl/parallel.cpp | 4 ++-- src/dynarmic/frontend/A32/translate/impl/thumb32_multiply.cpp | 4 ++-- src/dynarmic/ir/ir_emitter.cpp | 4 ++-- src/dynarmic/ir/ir_emitter.h | 2 +- src/dynarmic/ir/opcodes.inc | 2 +- 7 files changed, 11 insertions(+), 11 deletions(-) diff --git a/src/dynarmic/backend/arm64/emit_arm64_packed.cpp b/src/dynarmic/backend/arm64/emit_arm64_packed.cpp index 5a10ba74..b1700d96 100644 --- a/src/dynarmic/backend/arm64/emit_arm64_packed.cpp +++ b/src/dynarmic/backend/arm64/emit_arm64_packed.cpp @@ -382,10 +382,10 @@ void EmitIR(oaknut::CodeGenerator& code, Emit } template<> -void EmitIR(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) { +void EmitIR(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) { EmitPackedOp(code, ctx, inst, [&](auto& Vresult, auto& Va, auto& Vb) { code.MOVI(D2, oaknut::RepImm{0b00001111}); - code.SABD(Vresult->B8(), Va->B8(), Vb->B8()); + code.UABD(Vresult->B8(), Va->B8(), Vb->B8()); code.AND(Vresult->B8(), Vresult->B8(), V2.B8()); // TODO: Zext tracking code.UADDLV(Vresult->toH(), Vresult->B8()); }); diff --git a/src/dynarmic/backend/x64/emit_x64_packed.cpp b/src/dynarmic/backend/x64/emit_x64_packed.cpp index 61b82f03..7a710cd0 100644 --- a/src/dynarmic/backend/x64/emit_x64_packed.cpp +++ b/src/dynarmic/backend/x64/emit_x64_packed.cpp @@ -646,7 +646,7 @@ void EmitX64::EmitPackedSaturatedSubS16(EmitContext& ctx, IR::Inst* inst) { EmitPackedOperation(code, ctx, inst, &Xbyak::CodeGenerator::psubsw); } -void EmitX64::EmitPackedAbsDiffSumS8(EmitContext& ctx, IR::Inst* inst) { +void EmitX64::EmitPackedAbsDiffSumU8(EmitContext& ctx, IR::Inst* inst) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); const Xbyak::Xmm xmm_a = ctx.reg_alloc.UseScratchXmm(args[0]); diff --git a/src/dynarmic/frontend/A32/translate/impl/parallel.cpp b/src/dynarmic/frontend/A32/translate/impl/parallel.cpp index 2bbb010b..666cee2c 100644 --- a/src/dynarmic/frontend/A32/translate/impl/parallel.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/parallel.cpp @@ -177,7 +177,7 @@ bool TranslatorVisitor::arm_USAD8(Cond cond, Reg d, Reg m, Reg n) { return true; } - const auto result = ir.PackedAbsDiffSumS8(ir.GetRegister(n), ir.GetRegister(m)); + const auto result = ir.PackedAbsDiffSumU8(ir.GetRegister(n), ir.GetRegister(m)); ir.SetRegister(d, result); return true; } @@ -192,7 +192,7 @@ bool TranslatorVisitor::arm_USADA8(Cond cond, Reg d, Reg a, Reg m, Reg n) { return true; } - const auto tmp = ir.PackedAbsDiffSumS8(ir.GetRegister(n), ir.GetRegister(m)); + const auto tmp = ir.PackedAbsDiffSumU8(ir.GetRegister(n), ir.GetRegister(m)); const auto result = ir.AddWithCarry(ir.GetRegister(a), tmp, ir.Imm1(0)); ir.SetRegister(d, result); return true; diff --git a/src/dynarmic/frontend/A32/translate/impl/thumb32_multiply.cpp b/src/dynarmic/frontend/A32/translate/impl/thumb32_multiply.cpp index a40e67e1..587cbaaf 100644 --- a/src/dynarmic/frontend/A32/translate/impl/thumb32_multiply.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/thumb32_multiply.cpp @@ -288,7 +288,7 @@ bool TranslatorVisitor::thumb32_USAD8(Reg n, Reg d, Reg m) { const auto reg_m = ir.GetRegister(m); const auto reg_n = ir.GetRegister(n); - const auto result = ir.PackedAbsDiffSumS8(reg_n, reg_m); + const auto result = ir.PackedAbsDiffSumU8(reg_n, reg_m); ir.SetRegister(d, result); return true; @@ -302,7 +302,7 @@ bool TranslatorVisitor::thumb32_USADA8(Reg n, Reg a, Reg d, Reg m) { const auto reg_a = ir.GetRegister(a); const auto reg_m = ir.GetRegister(m); const auto reg_n = ir.GetRegister(n); - const auto tmp = ir.PackedAbsDiffSumS8(reg_n, reg_m); + const auto tmp = ir.PackedAbsDiffSumU8(reg_n, reg_m); const auto result = ir.AddWithCarry(reg_a, tmp, ir.Imm1(0)); ir.SetRegister(d, result); diff --git a/src/dynarmic/ir/ir_emitter.cpp b/src/dynarmic/ir/ir_emitter.cpp index 004b1303..45165098 100644 --- a/src/dynarmic/ir/ir_emitter.cpp +++ b/src/dynarmic/ir/ir_emitter.cpp @@ -848,8 +848,8 @@ U32 IREmitter::PackedSaturatedSubS16(const U32& a, const U32& b) { return Inst(Opcode::PackedSaturatedSubS16, a, b); } -U32 IREmitter::PackedAbsDiffSumS8(const U32& a, const U32& b) { - return Inst(Opcode::PackedAbsDiffSumS8, a, b); +U32 IREmitter::PackedAbsDiffSumU8(const U32& a, const U32& b) { + return Inst(Opcode::PackedAbsDiffSumU8, a, b); } U32 IREmitter::PackedSelect(const U32& ge, const U32& a, const U32& b) { diff --git a/src/dynarmic/ir/ir_emitter.h b/src/dynarmic/ir/ir_emitter.h index 0bdf99c5..3dc4cbb8 100644 --- a/src/dynarmic/ir/ir_emitter.h +++ b/src/dynarmic/ir/ir_emitter.h @@ -195,7 +195,7 @@ public: U32 PackedSaturatedAddS16(const U32& a, const U32& b); U32 PackedSaturatedSubU16(const U32& a, const U32& b); U32 PackedSaturatedSubS16(const U32& a, const U32& b); - U32 PackedAbsDiffSumS8(const U32& a, const U32& b); + U32 PackedAbsDiffSumU8(const U32& a, const U32& b); U32 PackedSelect(const U32& ge, const U32& a, const U32& b); U32 CRC32Castagnoli8(const U32& a, const U32& b); diff --git a/src/dynarmic/ir/opcodes.inc b/src/dynarmic/ir/opcodes.inc index c2954c31..c7dd2fef 100644 --- a/src/dynarmic/ir/opcodes.inc +++ b/src/dynarmic/ir/opcodes.inc @@ -250,7 +250,7 @@ OPCODE(PackedSaturatedAddU16, U32, U32, OPCODE(PackedSaturatedAddS16, U32, U32, U32 ) OPCODE(PackedSaturatedSubU16, U32, U32, U32 ) OPCODE(PackedSaturatedSubS16, U32, U32, U32 ) -OPCODE(PackedAbsDiffSumS8, U32, U32, U32 ) +OPCODE(PackedAbsDiffSumU8, U32, U32, U32 ) OPCODE(PackedSelect, U32, U32, U32, U32 ) // CRC instructions