diff --git a/src/frontend/A32/decoder/thumb32.h b/src/frontend/A32/decoder/thumb32.h index 48f4a386..b097f478 100644 --- a/src/frontend/A32/decoder/thumb32.h +++ b/src/frontend/A32/decoder/thumb32.h @@ -277,7 +277,7 @@ std::optional>> DecodeThumb32(u32 // Miscellaneous Operations //INST(&V::thumb32_QADD, "QADD", "111110101000----1111----1000----"), INST(&V::thumb32_QDADD, "QDADD", "111110101000nnnn1111dddd1001mmmm"), - //INST(&V::thumb32_QSUB, "QSUB", "111110101000----1111----1010----"), + INST(&V::thumb32_QSUB, "QSUB", "111110101000nnnn1111dddd1010mmmm"), INST(&V::thumb32_QDSUB, "QDSUB", "111110101000nnnn1111dddd1011mmmm"), INST(&V::thumb32_REV, "REV", "111110101001nnnn1111dddd1000mmmm"), INST(&V::thumb32_REV16, "REV16", "111110101001nnnn1111dddd1001mmmm"), diff --git a/src/frontend/A32/translate/impl/thumb32_misc.cpp b/src/frontend/A32/translate/impl/thumb32_misc.cpp index 9eed49cb..34c9e50e 100644 --- a/src/frontend/A32/translate/impl/thumb32_misc.cpp +++ b/src/frontend/A32/translate/impl/thumb32_misc.cpp @@ -51,6 +51,20 @@ bool ThumbTranslatorVisitor::thumb32_QDSUB(Reg n, Reg d, Reg m) { return true; } +bool ThumbTranslatorVisitor::thumb32_QSUB(Reg n, Reg d, Reg m) { + if (d == Reg::PC || n == Reg::PC || m == Reg::PC) { + return UnpredictableInstruction(); + } + + const auto reg_m = ir.GetRegister(m); + const auto reg_n = ir.GetRegister(n); + const auto result = ir.SignedSaturatedSub(reg_m, reg_n); + + ir.SetRegister(d, result.result); + ir.OrQFlag(result.overflow); + return true; +} + bool ThumbTranslatorVisitor::thumb32_RBIT(Reg n, Reg d, Reg m) { if (m != n || d == Reg::PC || m == Reg::PC) { return UnpredictableInstruction(); diff --git a/src/frontend/A32/translate/impl/translate_thumb.h b/src/frontend/A32/translate/impl/translate_thumb.h index 0fb9a5ca..9e8f40de 100644 --- a/src/frontend/A32/translate/impl/translate_thumb.h +++ b/src/frontend/A32/translate/impl/translate_thumb.h @@ -120,6 +120,7 @@ struct ThumbTranslatorVisitor final { bool thumb32_CLZ(Reg n, Reg d, Reg m); bool thumb32_QDADD(Reg n, Reg d, Reg m); bool thumb32_QDSUB(Reg n, Reg d, Reg m); + bool thumb32_QSUB(Reg n, Reg d, Reg m); bool thumb32_RBIT(Reg n, Reg d, Reg m); bool thumb32_REV(Reg n, Reg d, Reg m); bool thumb32_REV16(Reg n, Reg d, Reg m); diff --git a/tests/A32/fuzz_thumb.cpp b/tests/A32/fuzz_thumb.cpp index 90a57507..1cc596ba 100644 --- a/tests/A32/fuzz_thumb.cpp +++ b/tests/A32/fuzz_thumb.cpp @@ -383,6 +383,13 @@ TEST_CASE("Fuzz Thumb32 instructions set", "[JitX64][Thumb][Thumb32]") { const auto n = Common::Bits<16, 19>(inst); return d != 15 && m != 15 && n != 15; }), + ThumbInstGen("111110101000nnnn1111dddd1010mmmm", // QSUB + [](u32 inst) { + const auto d = Common::Bits<8, 11>(inst); + const auto m = Common::Bits<0, 3>(inst); + const auto n = Common::Bits<16, 19>(inst); + return d != 15 && m != 15 && n != 15; + }), ThumbInstGen("111110101001nnnn1111dddd1010mmmm", // RBIT [](u32 inst) { const auto d = Common::Bits<8, 11>(inst);