From ce6b5f8210f8932a5cf91780eb861398e971f476 Mon Sep 17 00:00:00 2001 From: MerryMage Date: Sun, 7 Aug 2016 01:27:18 +0100 Subject: [PATCH] VFP: Implement VABS --- src/backend_x64/emit_x64.cpp | 16 ++++++++++++++++ src/backend_x64/routines.cpp | 2 ++ src/backend_x64/routines.h | 4 ++++ src/frontend/decoder/vfp2.h | 2 +- src/frontend/disassembler/disassembler_arm.cpp | 4 ++++ src/frontend/ir/ir_emitter.cpp | 8 ++++++++ src/frontend/ir/ir_emitter.h | 2 ++ src/frontend/ir/opcodes.inc | 2 ++ .../translate/translate_arm/translate_arm.h | 3 +++ src/frontend/translate/translate_arm/vfp2.cpp | 17 +++++++++++++++++ 10 files changed, 59 insertions(+), 1 deletion(-) diff --git a/src/backend_x64/emit_x64.cpp b/src/backend_x64/emit_x64.cpp index 861cde55..d4e0fd2d 100644 --- a/src/backend_x64/emit_x64.cpp +++ b/src/backend_x64/emit_x64.cpp @@ -1090,6 +1090,22 @@ static void DefaultNaN64(XEmitter* code, Routines* routines, X64Reg xmm_value) { code->SetJumpTarget(fixup); } +void EmitX64::EmitFPAbs32(IR::Block& block, IR::Inst* inst) { + IR::Value a = inst->GetArg(0); + + X64Reg result = reg_alloc.UseDefRegister(a, inst, any_xmm); + + code->PAND(result, routines->MFloatNonSignMask32()); +} + +void EmitX64::EmitFPAbs64(IR::Block& block, IR::Inst* inst) { + IR::Value a = inst->GetArg(0); + + X64Reg result = reg_alloc.UseDefRegister(a, inst, any_xmm); + + code->PAND(result, routines->MFloatNonSignMask64()); +} + void EmitX64::EmitFPAdd32(IR::Block& block, IR::Inst* inst) { IR::Value a = inst->GetArg(0); IR::Value b = inst->GetArg(1); diff --git a/src/backend_x64/routines.cpp b/src/backend_x64/routines.cpp index de1cf6d1..f0f2dce0 100644 --- a/src/backend_x64/routines.cpp +++ b/src/backend_x64/routines.cpp @@ -36,6 +36,8 @@ void Routines::GenConstants() { Write32(0x80000000u); const_FloatNaN32 = AlignCode16(); Write32(0x7fc00000u); + const_FloatNonSignMask32 = AlignCode16(); + Write64(0x7fffffffu); const_FloatNegativeZero64 = AlignCode16(); Write64(0x8000000000000000u); const_FloatNaN64 = AlignCode16(); diff --git a/src/backend_x64/routines.h b/src/backend_x64/routines.h index 88117552..43705ac0 100644 --- a/src/backend_x64/routines.h +++ b/src/backend_x64/routines.h @@ -25,6 +25,9 @@ public: Gen::OpArg MFloatNaN32() const { return Gen::M(const_FloatNaN32); } + Gen::OpArg MFloatNonSignMask32() const { + return Gen::M(const_FloatNonSignMask32); + } Gen::OpArg MFloatNegativeZero64() const { return Gen::M(const_FloatNegativeZero64); } @@ -41,6 +44,7 @@ public: private: const u8* const_FloatNegativeZero32; const u8* const_FloatNaN32; + const u8* const_FloatNonSignMask32; const u8* const_FloatNegativeZero64; const u8* const_FloatNaN64; const u8* const_FloatNonSignMask64; diff --git a/src/frontend/decoder/vfp2.h b/src/frontend/decoder/vfp2.h index 8989549e..0bae062c 100644 --- a/src/frontend/decoder/vfp2.h +++ b/src/frontend/decoder/vfp2.h @@ -77,7 +77,7 @@ boost::optional&> DecodeVFP2(u32 instruction) { // Floating-point other instructions // VMOV_imm // VMOV_reg - // VABS + INST(&V::vfp2_VABS, "VABS", "cccc11101D110000dddd101z11M0mmmm"), // VNEG // VSQRT // VCMP diff --git a/src/frontend/disassembler/disassembler_arm.cpp b/src/frontend/disassembler/disassembler_arm.cpp index d0fb8a90..fbb28d2c 100644 --- a/src/frontend/disassembler/disassembler_arm.cpp +++ b/src/frontend/disassembler/disassembler_arm.cpp @@ -563,6 +563,10 @@ public: std::string vfp2_VADD(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) { return Common::StringFromFormat("vadd%s.%s %s, %s, %s", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D).c_str(), FPRegStr(sz, Vn, N).c_str(), FPRegStr(sz, Vm, M).c_str()); } + + std::string vfp2_VABS(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm) { + return Common::StringFromFormat("vadd%s.%s %s, %s", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D).c_str(), FPRegStr(sz, Vm, M).c_str()); + } }; std::string DisassembleArm(u32 instruction) { diff --git a/src/frontend/ir/ir_emitter.cpp b/src/frontend/ir/ir_emitter.cpp index d3bf1044..19ca9d06 100644 --- a/src/frontend/ir/ir_emitter.cpp +++ b/src/frontend/ir/ir_emitter.cpp @@ -274,6 +274,14 @@ IR::Value IREmitter::ByteReverseDual(const IR::Value& a) { return Inst(IR::Opcode::ByteReverseDual, {a}); } +IR::Value IREmitter::FPAbs32(const IR::Value& a) { + return Inst(IR::Opcode::FPAbs32, {a}); +} + +IR::Value IREmitter::FPAbs64(const IR::Value& a) { + return Inst(IR::Opcode::FPAbs64, {a}); +} + IR::Value IREmitter::FPAdd32(const IR::Value& a, const IR::Value& b, bool fpscr_controlled) { ASSERT(fpscr_controlled); return Inst(IR::Opcode::FPAdd32, {a, b}); diff --git a/src/frontend/ir/ir_emitter.h b/src/frontend/ir/ir_emitter.h index c0e312c9..3dfaa057 100644 --- a/src/frontend/ir/ir_emitter.h +++ b/src/frontend/ir/ir_emitter.h @@ -92,6 +92,8 @@ public: IR::Value ByteReverseHalf(const IR::Value& a); IR::Value ByteReverseDual(const IR::Value& a); + IR::Value FPAbs32(const IR::Value& a); + IR::Value FPAbs64(const IR::Value& a); IR::Value FPAdd32(const IR::Value& a, const IR::Value& b, bool fpscr_controlled); IR::Value FPAdd64(const IR::Value& a, const IR::Value& b, bool fpscr_controlled); diff --git a/src/frontend/ir/opcodes.inc b/src/frontend/ir/opcodes.inc index 7c17a45e..982cbf51 100644 --- a/src/frontend/ir/opcodes.inc +++ b/src/frontend/ir/opcodes.inc @@ -60,6 +60,8 @@ OPCODE(ByteReverseHalf, T::U16, T::U16 OPCODE(ByteReverseDual, T::U64, T::U64 ) // Floating-point +OPCODE(FPAbs32, T::F32, T::F32 ) +OPCODE(FPAbs64, T::F64, T::F64 ) OPCODE(FPAdd32, T::F32, T::F32, T::F32 ) OPCODE(FPAdd64, T::F64, T::F64, T::F64 ) diff --git a/src/frontend/translate/translate_arm/translate_arm.h b/src/frontend/translate/translate_arm/translate_arm.h index d49e63f7..6de08443 100644 --- a/src/frontend/translate/translate_arm/translate_arm.h +++ b/src/frontend/translate/translate_arm/translate_arm.h @@ -320,6 +320,9 @@ struct ArmTranslatorVisitor final { // Floating-point three-register data processing instructions bool vfp2_VADD(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm); + + // Floating-point misc instructions + bool vfp2_VABS(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm); }; } // namespace Arm diff --git a/src/frontend/translate/translate_arm/vfp2.cpp b/src/frontend/translate/translate_arm/vfp2.cpp index ff104e56..0277f050 100644 --- a/src/frontend/translate/translate_arm/vfp2.cpp +++ b/src/frontend/translate/translate_arm/vfp2.cpp @@ -36,5 +36,22 @@ bool ArmTranslatorVisitor::vfp2_VADD(Cond cond, bool D, size_t Vn, size_t Vd, bo return true; } +bool ArmTranslatorVisitor::vfp2_VABS(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm) { + if (ir.current_location.FPSCR_Len() != 1 || ir.current_location.FPSCR_Stride() != 1) + return InterpretThisInstruction(); // TODO: Vectorised floating point instructions + + ExtReg d = ToExtReg(sz, Vd, D); + ExtReg m = ToExtReg(sz, Vm, M); + // VABS.{F32,F64} <{S,D}d>, <{S,D}m> + if (ConditionPassed(cond)) { + auto a = ir.GetExtendedRegister(m); + auto result = sz + ? ir.FPAbs64(a) + : ir.FPAbs32(a); + ir.SetExtendedRegister(d, result); + } + return true; +} + } // namespace Arm } // namespace Dynarmic