From d1f5b084b4300c37165755db8790b096f07f1ec0 Mon Sep 17 00:00:00 2001 From: Lioncash Date: Thu, 19 Apr 2018 15:24:08 -0400 Subject: [PATCH] A64: Handle S32->F32 case for SCVTF (vector) --- src/frontend/A64/decoder/a64.inc | 2 +- .../translate/impl/simd_two_register_misc.cpp | 19 +++++++++++++++++++ 2 files changed, 20 insertions(+), 1 deletion(-) diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc index 150c119f..e56d83ae 100644 --- a/src/frontend/A64/decoder/a64.inc +++ b/src/frontend/A64/decoder/a64.inc @@ -592,7 +592,7 @@ INST(XTN, "XTN, XTN2", "0Q001 //INST(FCVTAS_3, "FCVTAS (vector)", "0Q00111001111001110010nnnnnddddd") //INST(FCVTAS_4, "FCVTAS (vector)", "0Q0011100z100001110010nnnnnddddd") //INST(SCVTF_int_3, "SCVTF (vector, integer)", "0Q00111001111001110110nnnnnddddd") -//INST(SCVTF_int_4, "SCVTF (vector, integer)", "0Q0011100z100001110110nnnnnddddd") +INST(SCVTF_int_4, "SCVTF (vector, integer)", "0Q0011100z100001110110nnnnnddddd") //INST(FCMGT_zero_3, "FCMGT (zero)", "0Q00111011111000110010nnnnnddddd") //INST(FCMGT_zero_4, "FCMGT (zero)", "0Q0011101z100000110010nnnnnddddd") //INST(FCMEQ_zero_3, "FCMEQ (zero)", "0Q00111011111000110110nnnnnddddd") diff --git a/src/frontend/A64/translate/impl/simd_two_register_misc.cpp b/src/frontend/A64/translate/impl/simd_two_register_misc.cpp index 3c045c5e..c4d5ed4a 100644 --- a/src/frontend/A64/translate/impl/simd_two_register_misc.cpp +++ b/src/frontend/A64/translate/impl/simd_two_register_misc.cpp @@ -243,4 +243,23 @@ bool TranslatorVisitor::REV64_asimd(bool Q, Imm<2> size, Vec Vn, Vec Vd) { return true; } +bool TranslatorVisitor::SCVTF_int_4(bool Q, bool sz, Vec Vn, Vec Vd) { + if (sz && !Q) { + return ReservedValue(); + } + + if (sz) { + // TODO: Implement + return InterpretThisInstruction(); + } + + const size_t datasize = Q ? 128 : 64; + + const IR::U128 operand = V(datasize, Vn); + const IR::U128 result = ir.FPVectorS32ToSingle(operand); + + V(datasize, Vd, result); + return true; +} + } // namespace Dynarmic::A64