From d3664b03fea4b4f9fa71ce5b9e1a6ce95f22f7bb Mon Sep 17 00:00:00 2001 From: MerryMage Date: Fri, 19 Jun 2020 22:46:19 +0100 Subject: [PATCH] ir_emitter: Default fpcr_controlled arguments to true --- src/frontend/A32/translate/impl/vfp.cpp | 36 +++++++++---------- .../translate/impl/floating_point_compare.cpp | 2 +- .../floating_point_conditional_compare.cpp | 2 +- ...g_point_data_processing_three_register.cpp | 8 ++--- ...ing_point_data_processing_two_register.cpp | 18 +++++----- .../A64/translate/impl/simd_across_lanes.cpp | 8 ++--- .../translate/impl/simd_scalar_pairwise.cpp | 10 +++--- .../translate/impl/simd_scalar_three_same.cpp | 2 +- .../impl/simd_scalar_x_indexed_element.cpp | 6 ++-- .../translate/impl/simd_three_same_extra.cpp | 12 +++---- .../impl/simd_vector_x_indexed_element.cpp | 6 ++-- src/frontend/ir/ir_emitter.h | 20 +++++------ 12 files changed, 62 insertions(+), 68 deletions(-) diff --git a/src/frontend/A32/translate/impl/vfp.cpp b/src/frontend/A32/translate/impl/vfp.cpp index 77341794..33f8578a 100644 --- a/src/frontend/A32/translate/impl/vfp.cpp +++ b/src/frontend/A32/translate/impl/vfp.cpp @@ -97,7 +97,7 @@ bool ArmTranslatorVisitor::vfp_VADD(Cond cond, bool D, size_t Vn, size_t Vd, boo return EmitVfpVectorOperation(sz, d, n, m, [this](ExtReg d, ExtReg n, ExtReg m) { const auto reg_n = ir.GetExtendedRegister(n); const auto reg_m = ir.GetExtendedRegister(m); - const auto result = ir.FPAdd(reg_n, reg_m, true); + const auto result = ir.FPAdd(reg_n, reg_m); ir.SetExtendedRegister(d, result); }); } @@ -116,7 +116,7 @@ bool ArmTranslatorVisitor::vfp_VSUB(Cond cond, bool D, size_t Vn, size_t Vd, boo return EmitVfpVectorOperation(sz, d, n, m, [this](ExtReg d, ExtReg n, ExtReg m) { const auto reg_n = ir.GetExtendedRegister(n); const auto reg_m = ir.GetExtendedRegister(m); - const auto result = ir.FPSub(reg_n, reg_m, true); + const auto result = ir.FPSub(reg_n, reg_m); ir.SetExtendedRegister(d, result); }); } @@ -135,7 +135,7 @@ bool ArmTranslatorVisitor::vfp_VMUL(Cond cond, bool D, size_t Vn, size_t Vd, boo return EmitVfpVectorOperation(sz, d, n, m, [this](ExtReg d, ExtReg n, ExtReg m) { const auto reg_n = ir.GetExtendedRegister(n); const auto reg_m = ir.GetExtendedRegister(m); - const auto result = ir.FPMul(reg_n, reg_m, true); + const auto result = ir.FPMul(reg_n, reg_m); ir.SetExtendedRegister(d, result); }); } @@ -155,7 +155,7 @@ bool ArmTranslatorVisitor::vfp_VMLA(Cond cond, bool D, size_t Vn, size_t Vd, boo const auto reg_n = ir.GetExtendedRegister(n); const auto reg_m = ir.GetExtendedRegister(m); const auto reg_d = ir.GetExtendedRegister(d); - const auto result = ir.FPAdd(reg_d, ir.FPMul(reg_n, reg_m, true), true); + const auto result = ir.FPAdd(reg_d, ir.FPMul(reg_n, reg_m)); ir.SetExtendedRegister(d, result); }); } @@ -175,7 +175,7 @@ bool ArmTranslatorVisitor::vfp_VMLS(Cond cond, bool D, size_t Vn, size_t Vd, boo const auto reg_n = ir.GetExtendedRegister(n); const auto reg_m = ir.GetExtendedRegister(m); const auto reg_d = ir.GetExtendedRegister(d); - const auto result = ir.FPAdd(reg_d, ir.FPNeg(ir.FPMul(reg_n, reg_m, true)), true); + const auto result = ir.FPAdd(reg_d, ir.FPNeg(ir.FPMul(reg_n, reg_m))); ir.SetExtendedRegister(d, result); }); } @@ -194,7 +194,7 @@ bool ArmTranslatorVisitor::vfp_VNMUL(Cond cond, bool D, size_t Vn, size_t Vd, bo return EmitVfpVectorOperation(sz, d, n, m, [this](ExtReg d, ExtReg n, ExtReg m) { const auto reg_n = ir.GetExtendedRegister(n); const auto reg_m = ir.GetExtendedRegister(m); - const auto result = ir.FPNeg(ir.FPMul(reg_n, reg_m, true)); + const auto result = ir.FPNeg(ir.FPMul(reg_n, reg_m)); ir.SetExtendedRegister(d, result); }); } @@ -214,7 +214,7 @@ bool ArmTranslatorVisitor::vfp_VNMLA(Cond cond, bool D, size_t Vn, size_t Vd, bo const auto reg_n = ir.GetExtendedRegister(n); const auto reg_m = ir.GetExtendedRegister(m); const auto reg_d = ir.GetExtendedRegister(d); - const auto result = ir.FPAdd(ir.FPNeg(reg_d), ir.FPNeg(ir.FPMul(reg_n, reg_m, true)), true); + const auto result = ir.FPAdd(ir.FPNeg(reg_d), ir.FPNeg(ir.FPMul(reg_n, reg_m))); ir.SetExtendedRegister(d, result); }); } @@ -234,7 +234,7 @@ bool ArmTranslatorVisitor::vfp_VNMLS(Cond cond, bool D, size_t Vn, size_t Vd, bo const auto reg_n = ir.GetExtendedRegister(n); const auto reg_m = ir.GetExtendedRegister(m); const auto reg_d = ir.GetExtendedRegister(d); - const auto result = ir.FPAdd(ir.FPNeg(reg_d), ir.FPMul(reg_n, reg_m, true), true); + const auto result = ir.FPAdd(ir.FPNeg(reg_d), ir.FPMul(reg_n, reg_m)); ir.SetExtendedRegister(d, result); }); } @@ -253,7 +253,7 @@ bool ArmTranslatorVisitor::vfp_VDIV(Cond cond, bool D, size_t Vn, size_t Vd, boo return EmitVfpVectorOperation(sz, d, n, m, [this](ExtReg d, ExtReg n, ExtReg m) { const auto reg_n = ir.GetExtendedRegister(n); const auto reg_m = ir.GetExtendedRegister(m); - const auto result = ir.FPDiv(reg_n, reg_m, true); + const auto result = ir.FPDiv(reg_n, reg_m); ir.SetExtendedRegister(d, result); }); } @@ -273,7 +273,7 @@ bool ArmTranslatorVisitor::vfp_VFNMS(Cond cond, bool D, size_t Vn, size_t Vd, bo const auto reg_n = ir.GetExtendedRegister(n); const auto reg_m = ir.GetExtendedRegister(m); const auto reg_d = ir.GetExtendedRegister(d); - const auto result = ir.FPMulAdd(ir.FPNeg(reg_d), reg_n, reg_m, true); + const auto result = ir.FPMulAdd(ir.FPNeg(reg_d), reg_n, reg_m); ir.SetExtendedRegister(d, result); }); } @@ -293,7 +293,7 @@ bool ArmTranslatorVisitor::vfp_VFNMA(Cond cond, bool D, size_t Vn, size_t Vd, bo const auto reg_n = ir.GetExtendedRegister(n); const auto reg_m = ir.GetExtendedRegister(m); const auto reg_d = ir.GetExtendedRegister(d); - const auto result = ir.FPMulAdd(ir.FPNeg(reg_d), ir.FPNeg(reg_n), reg_m, true); + const auto result = ir.FPMulAdd(ir.FPNeg(reg_d), ir.FPNeg(reg_n), reg_m); ir.SetExtendedRegister(d, result); }); } @@ -313,7 +313,7 @@ bool ArmTranslatorVisitor::vfp_VFMA(Cond cond, bool D, size_t Vn, size_t Vd, boo const auto reg_n = ir.GetExtendedRegister(n); const auto reg_m = ir.GetExtendedRegister(m); const auto reg_d = ir.GetExtendedRegister(d); - const auto result = ir.FPMulAdd(reg_d, reg_n, reg_m, true); + const auto result = ir.FPMulAdd(reg_d, reg_n, reg_m); ir.SetExtendedRegister(d, result); }); } @@ -333,7 +333,7 @@ bool ArmTranslatorVisitor::vfp_VFMS(Cond cond, bool D, size_t Vn, size_t Vd, boo const auto reg_n = ir.GetExtendedRegister(n); const auto reg_m = ir.GetExtendedRegister(m); const auto reg_d = ir.GetExtendedRegister(d); - const auto result = ir.FPMulAdd(reg_d, ir.FPNeg(reg_n), reg_m, true); + const auto result = ir.FPMulAdd(reg_d, ir.FPNeg(reg_n), reg_m); ir.SetExtendedRegister(d, result); }); } @@ -365,7 +365,7 @@ bool ArmTranslatorVisitor::vfp_VMAXNM(bool D, size_t Vn, size_t Vd, bool sz, boo return EmitVfpVectorOperation(sz, d, n, m, [this](ExtReg d, ExtReg n, ExtReg m) { const auto reg_n = ir.GetExtendedRegister(n); const auto reg_m = ir.GetExtendedRegister(m); - const auto result = ir.FPMaxNumeric(reg_n, reg_m, true); + const auto result = ir.FPMaxNumeric(reg_n, reg_m); ir.SetExtendedRegister(d, result); }); } @@ -380,7 +380,7 @@ bool ArmTranslatorVisitor::vfp_VMINNM(bool D, size_t Vn, size_t Vd, bool sz, boo return EmitVfpVectorOperation(sz, d, n, m, [this](ExtReg d, ExtReg n, ExtReg m) { const auto reg_n = ir.GetExtendedRegister(n); const auto reg_m = ir.GetExtendedRegister(m); - const auto result = ir.FPMinNumeric(reg_n, reg_m, true); + const auto result = ir.FPMinNumeric(reg_n, reg_m); ir.SetExtendedRegister(d, result); }); } @@ -695,7 +695,7 @@ bool ArmTranslatorVisitor::vfp_VCMP(Cond cond, bool D, size_t Vd, bool sz, bool const auto exc_on_qnan = E; const auto reg_d = ir.GetExtendedRegister(d); const auto reg_m = ir.GetExtendedRegister(m); - const auto nzcv = ir.FPCompare(reg_d, reg_m, exc_on_qnan, true); + const auto nzcv = ir.FPCompare(reg_d, reg_m, exc_on_qnan); ir.SetFpscrNZCV(nzcv); return true; @@ -713,10 +713,10 @@ bool ArmTranslatorVisitor::vfp_VCMP_zero(Cond cond, bool D, size_t Vd, bool sz, const auto reg_d = ir.GetExtendedRegister(d); if (sz) { - const auto nzcv = ir.FPCompare(reg_d, ir.Imm64(0), exc_on_qnan, true); + const auto nzcv = ir.FPCompare(reg_d, ir.Imm64(0), exc_on_qnan); ir.SetFpscrNZCV(nzcv); } else { - const auto nzcv = ir.FPCompare(reg_d, ir.Imm32(0), exc_on_qnan, true); + const auto nzcv = ir.FPCompare(reg_d, ir.Imm32(0), exc_on_qnan); ir.SetFpscrNZCV(nzcv); } diff --git a/src/frontend/A64/translate/impl/floating_point_compare.cpp b/src/frontend/A64/translate/impl/floating_point_compare.cpp index 84e21928..80cf4694 100644 --- a/src/frontend/A64/translate/impl/floating_point_compare.cpp +++ b/src/frontend/A64/translate/impl/floating_point_compare.cpp @@ -21,7 +21,7 @@ bool FPCompare(TranslatorVisitor& v, Imm<2> type, Vec Vm, Vec Vn, bool exc_on_qn operand2 = v.V_scalar(*datasize, Vm); } - const auto nzcv = v.ir.FPCompare(operand1, operand2, exc_on_qnan, true); + const auto nzcv = v.ir.FPCompare(operand1, operand2, exc_on_qnan); v.ir.SetNZCV(nzcv); return true; } diff --git a/src/frontend/A64/translate/impl/floating_point_conditional_compare.cpp b/src/frontend/A64/translate/impl/floating_point_conditional_compare.cpp index e6b3f634..329722e2 100644 --- a/src/frontend/A64/translate/impl/floating_point_conditional_compare.cpp +++ b/src/frontend/A64/translate/impl/floating_point_conditional_compare.cpp @@ -17,7 +17,7 @@ bool FPCompare(TranslatorVisitor& v, Imm<2> type, Vec Vm, Cond cond, Vec Vn, Imm const IR::U32U64 operand1 = v.V_scalar(*datasize, Vn); const IR::U32U64 operand2 = v.V_scalar(*datasize, Vm); - const IR::NZCV then_flags = v.ir.FPCompare(operand1, operand2, exc_on_qnan, true); + const IR::NZCV then_flags = v.ir.FPCompare(operand1, operand2, exc_on_qnan); const IR::NZCV else_flags = v.ir.NZCVFromPackedFlags(v.ir.Imm32(flags)); v.ir.SetNZCV(v.ir.ConditionalSelect(cond, then_flags, else_flags)); return true; diff --git a/src/frontend/A64/translate/impl/floating_point_data_processing_three_register.cpp b/src/frontend/A64/translate/impl/floating_point_data_processing_three_register.cpp index 018422a6..66c3c937 100644 --- a/src/frontend/A64/translate/impl/floating_point_data_processing_three_register.cpp +++ b/src/frontend/A64/translate/impl/floating_point_data_processing_three_register.cpp @@ -16,7 +16,7 @@ bool TranslatorVisitor::FMADD_float(Imm<2> type, Vec Vm, Vec Va, Vec Vn, Vec Vd) const IR::U16U32U64 operanda = V_scalar(*datasize, Va); const IR::U16U32U64 operand1 = V_scalar(*datasize, Vn); const IR::U16U32U64 operand2 = V_scalar(*datasize, Vm); - const IR::U16U32U64 result = ir.FPMulAdd(operanda, operand1, operand2, true); + const IR::U16U32U64 result = ir.FPMulAdd(operanda, operand1, operand2); V_scalar(*datasize, Vd, result); return true; } @@ -30,7 +30,7 @@ bool TranslatorVisitor::FMSUB_float(Imm<2> type, Vec Vm, Vec Va, Vec Vn, Vec Vd) const IR::U16U32U64 operanda = V_scalar(*datasize, Va); const IR::U16U32U64 operand1 = V_scalar(*datasize, Vn); const IR::U16U32U64 operand2 = V_scalar(*datasize, Vm); - const IR::U16U32U64 result = ir.FPMulAdd(operanda, ir.FPNeg(operand1), operand2, true); + const IR::U16U32U64 result = ir.FPMulAdd(operanda, ir.FPNeg(operand1), operand2); V_scalar(*datasize, Vd, result); return true; } @@ -44,7 +44,7 @@ bool TranslatorVisitor::FNMADD_float(Imm<2> type, Vec Vm, Vec Va, Vec Vn, Vec Vd const IR::U16U32U64 operanda = V_scalar(*datasize, Va); const IR::U16U32U64 operand1 = V_scalar(*datasize, Vn); const IR::U16U32U64 operand2 = V_scalar(*datasize, Vm); - const IR::U16U32U64 result = ir.FPMulAdd(ir.FPNeg(operanda), ir.FPNeg(operand1), operand2, true); + const IR::U16U32U64 result = ir.FPMulAdd(ir.FPNeg(operanda), ir.FPNeg(operand1), operand2); V_scalar(*datasize, Vd, result); return true; } @@ -58,7 +58,7 @@ bool TranslatorVisitor::FNMSUB_float(Imm<2> type, Vec Vm, Vec Va, Vec Vn, Vec Vd const IR::U16U32U64 operanda = V_scalar(*datasize, Va); const IR::U16U32U64 operand1 = V_scalar(*datasize, Vn); const IR::U16U32U64 operand2 = V_scalar(*datasize, Vm); - const IR::U16U32U64 result = ir.FPMulAdd(ir.FPNeg(operanda), operand1, operand2, true); + const IR::U16U32U64 result = ir.FPMulAdd(ir.FPNeg(operanda), operand1, operand2); V_scalar(*datasize, Vd, result); return true; } diff --git a/src/frontend/A64/translate/impl/floating_point_data_processing_two_register.cpp b/src/frontend/A64/translate/impl/floating_point_data_processing_two_register.cpp index dda29081..e29eb898 100644 --- a/src/frontend/A64/translate/impl/floating_point_data_processing_two_register.cpp +++ b/src/frontend/A64/translate/impl/floating_point_data_processing_two_register.cpp @@ -16,7 +16,7 @@ bool TranslatorVisitor::FMUL_float(Imm<2> type, Vec Vm, Vec Vn, Vec Vd) { const IR::U32U64 operand1 = V_scalar(*datasize, Vn); const IR::U32U64 operand2 = V_scalar(*datasize, Vm); - const IR::U32U64 result = ir.FPMul(operand1, operand2, true); + const IR::U32U64 result = ir.FPMul(operand1, operand2); V_scalar(*datasize, Vd, result); return true; @@ -31,7 +31,7 @@ bool TranslatorVisitor::FDIV_float(Imm<2> type, Vec Vm, Vec Vn, Vec Vd) { const IR::U32U64 operand1 = V_scalar(*datasize, Vn); const IR::U32U64 operand2 = V_scalar(*datasize, Vm); - const IR::U32U64 result = ir.FPDiv(operand1, operand2, true); + const IR::U32U64 result = ir.FPDiv(operand1, operand2); V_scalar(*datasize, Vd, result); return true; @@ -46,7 +46,7 @@ bool TranslatorVisitor::FADD_float(Imm<2> type, Vec Vm, Vec Vn, Vec Vd) { const IR::U32U64 operand1 = V_scalar(*datasize, Vn); const IR::U32U64 operand2 = V_scalar(*datasize, Vm); - const IR::U32U64 result = ir.FPAdd(operand1, operand2, true); + const IR::U32U64 result = ir.FPAdd(operand1, operand2); V_scalar(*datasize, Vd, result); return true; @@ -61,7 +61,7 @@ bool TranslatorVisitor::FSUB_float(Imm<2> type, Vec Vm, Vec Vn, Vec Vd) { const IR::U32U64 operand1 = V_scalar(*datasize, Vn); const IR::U32U64 operand2 = V_scalar(*datasize, Vm); - const IR::U32U64 result = ir.FPSub(operand1, operand2, true); + const IR::U32U64 result = ir.FPSub(operand1, operand2); V_scalar(*datasize, Vd, result); return true; @@ -76,7 +76,7 @@ bool TranslatorVisitor::FMAX_float(Imm<2> type, Vec Vm, Vec Vn, Vec Vd) { const IR::U32U64 operand1 = V_scalar(*datasize, Vn); const IR::U32U64 operand2 = V_scalar(*datasize, Vm); - const IR::U32U64 result = ir.FPMax(operand1, operand2, true); + const IR::U32U64 result = ir.FPMax(operand1, operand2); V_scalar(*datasize, Vd, result); return true; @@ -91,7 +91,7 @@ bool TranslatorVisitor::FMIN_float(Imm<2> type, Vec Vm, Vec Vn, Vec Vd) { const IR::U32U64 operand1 = V_scalar(*datasize, Vn); const IR::U32U64 operand2 = V_scalar(*datasize, Vm); - const IR::U32U64 result = ir.FPMin(operand1, operand2, true); + const IR::U32U64 result = ir.FPMin(operand1, operand2); V_scalar(*datasize, Vd, result); return true; @@ -106,7 +106,7 @@ bool TranslatorVisitor::FMAXNM_float(Imm<2> type, Vec Vm, Vec Vn, Vec Vd) { const IR::U32U64 operand1 = V_scalar(*datasize, Vn); const IR::U32U64 operand2 = V_scalar(*datasize, Vm); - const IR::U32U64 result = ir.FPMaxNumeric(operand1, operand2, true); + const IR::U32U64 result = ir.FPMaxNumeric(operand1, operand2); V_scalar(*datasize, Vd, result); return true; @@ -121,7 +121,7 @@ bool TranslatorVisitor::FMINNM_float(Imm<2> type, Vec Vm, Vec Vn, Vec Vd) { const IR::U32U64 operand1 = V_scalar(*datasize, Vn); const IR::U32U64 operand2 = V_scalar(*datasize, Vm); - const IR::U32U64 result = ir.FPMinNumeric(operand1, operand2, true); + const IR::U32U64 result = ir.FPMinNumeric(operand1, operand2); V_scalar(*datasize, Vd, result); return true; @@ -136,7 +136,7 @@ bool TranslatorVisitor::FNMUL_float(Imm<2> type, Vec Vm, Vec Vn, Vec Vd) { const IR::U32U64 operand1 = V_scalar(*datasize, Vn); const IR::U32U64 operand2 = V_scalar(*datasize, Vm); - const IR::U32U64 result = ir.FPNeg(ir.FPMul(operand1, operand2, true)); + const IR::U32U64 result = ir.FPNeg(ir.FPMul(operand1, operand2)); V_scalar(*datasize, Vd, result); return true; diff --git a/src/frontend/A64/translate/impl/simd_across_lanes.cpp b/src/frontend/A64/translate/impl/simd_across_lanes.cpp index 22d7ab1e..62c4ef65 100644 --- a/src/frontend/A64/translate/impl/simd_across_lanes.cpp +++ b/src/frontend/A64/translate/impl/simd_across_lanes.cpp @@ -70,13 +70,13 @@ bool FPMinMax(TranslatorVisitor& v, bool Q, bool sz, Vec Vn, Vec Vd, MinMaxOpera const auto op = [&](const IR::U32U64& lhs, const IR::U32U64& rhs) { switch (operation) { case MinMaxOperation::Max: - return v.ir.FPMax(lhs, rhs, true); + return v.ir.FPMax(lhs, rhs); case MinMaxOperation::MaxNumeric: - return v.ir.FPMaxNumeric(lhs, rhs, true); + return v.ir.FPMaxNumeric(lhs, rhs); case MinMaxOperation::Min: - return v.ir.FPMin(lhs, rhs, true); + return v.ir.FPMin(lhs, rhs); case MinMaxOperation::MinNumeric: - return v.ir.FPMinNumeric(lhs, rhs, true); + return v.ir.FPMinNumeric(lhs, rhs); default: UNREACHABLE(); } diff --git a/src/frontend/A64/translate/impl/simd_scalar_pairwise.cpp b/src/frontend/A64/translate/impl/simd_scalar_pairwise.cpp index 1a24dd2e..b9df9649 100644 --- a/src/frontend/A64/translate/impl/simd_scalar_pairwise.cpp +++ b/src/frontend/A64/translate/impl/simd_scalar_pairwise.cpp @@ -23,13 +23,13 @@ bool FPPairwiseMinMax(TranslatorVisitor& v, bool sz, Vec Vn, Vec Vd, MinMaxOpera const IR::U32U64 result = [&] { switch (operation) { case MinMaxOperation::Max: - return v.ir.FPMax(element1, element2, true); + return v.ir.FPMax(element1, element2); case MinMaxOperation::MaxNumeric: - return v.ir.FPMaxNumeric(element1, element2, true); + return v.ir.FPMaxNumeric(element1, element2); case MinMaxOperation::Min: - return v.ir.FPMin(element1, element2, true); + return v.ir.FPMin(element1, element2); case MinMaxOperation::MinNumeric: - return v.ir.FPMinNumeric(element1, element2, true); + return v.ir.FPMinNumeric(element1, element2); default: UNREACHABLE(); } @@ -57,7 +57,7 @@ bool TranslatorVisitor::FADDP_pair_2(bool size, Vec Vn, Vec Vd) { const IR::U32U64 operand1 = ir.VectorGetElement(esize, V(128, Vn), 0); const IR::U32U64 operand2 = ir.VectorGetElement(esize, V(128, Vn), 1); - const IR::U128 result = ir.ZeroExtendToQuad(ir.FPAdd(operand1, operand2, true)); + const IR::U128 result = ir.ZeroExtendToQuad(ir.FPAdd(operand1, operand2)); V(128, Vd, result); return true; } diff --git a/src/frontend/A64/translate/impl/simd_scalar_three_same.cpp b/src/frontend/A64/translate/impl/simd_scalar_three_same.cpp index 48deeb61..007d0ae1 100644 --- a/src/frontend/A64/translate/impl/simd_scalar_three_same.cpp +++ b/src/frontend/A64/translate/impl/simd_scalar_three_same.cpp @@ -275,7 +275,7 @@ bool TranslatorVisitor::FABD_2(bool sz, Vec Vm, Vec Vn, Vec Vd) { const IR::U32U64 operand1 = V_scalar(esize, Vn); const IR::U32U64 operand2 = V_scalar(esize, Vm); - const IR::U32U64 result = ir.FPAbs(ir.FPSub(operand1, operand2, true)); + const IR::U32U64 result = ir.FPAbs(ir.FPSub(operand1, operand2)); V_scalar(esize, Vd, result); return true; diff --git a/src/frontend/A64/translate/impl/simd_scalar_x_indexed_element.cpp b/src/frontend/A64/translate/impl/simd_scalar_x_indexed_element.cpp index 904ec7ad..5c58e4e8 100644 --- a/src/frontend/A64/translate/impl/simd_scalar_x_indexed_element.cpp +++ b/src/frontend/A64/translate/impl/simd_scalar_x_indexed_element.cpp @@ -39,7 +39,7 @@ bool MultiplyByElement(TranslatorVisitor& v, bool sz, Imm<1> L, Imm<1> M, Imm<4> IR::U32U64 operand1 = v.V_scalar(esize, Vn); if (extra_behavior == ExtraBehavior::None) { - return v.ir.FPMul(operand1, element, true); + return v.ir.FPMul(operand1, element); } if (extra_behavior == ExtraBehavior::MultiplyExtended) { @@ -51,7 +51,7 @@ bool MultiplyByElement(TranslatorVisitor& v, bool sz, Imm<1> L, Imm<1> M, Imm<4> } const IR::U32U64 operand2 = v.V_scalar(esize, Vd); - return v.ir.FPMulAdd(operand2, operand1, element, true); + return v.ir.FPMulAdd(operand2, operand1, element); }(); v.V_scalar(esize, Vd, result); @@ -85,7 +85,7 @@ bool MultiplyByElementHalfPrecision(TranslatorVisitor& v, Imm<1> L, Imm<1> M, Im } const IR::U16 operand2 = v.V_scalar(esize, Vd); - return v.ir.FPMulAdd(operand2, operand1, element, true); + return v.ir.FPMulAdd(operand2, operand1, element); }(); v.V_scalar(esize, Vd, result); diff --git a/src/frontend/A64/translate/impl/simd_three_same_extra.cpp b/src/frontend/A64/translate/impl/simd_three_same_extra.cpp index 07560488..f637123f 100644 --- a/src/frontend/A64/translate/impl/simd_three_same_extra.cpp +++ b/src/frontend/A64/translate/impl/simd_three_same_extra.cpp @@ -115,10 +115,8 @@ bool TranslatorVisitor::FCMLA_vec(bool Q, Imm<2> size, Vec Vm, Imm<2> rot, Vec V const IR::U32U64 operand3_elem1 = ir.VectorGetElement(esize, operand3, first); const IR::U32U64 operand3_elem2 = ir.VectorGetElement(esize, operand3, second); - result = ir.VectorSetElement(esize, result, first, - ir.FPMulAdd(operand3_elem1, element2, element1, true)); - result = ir.VectorSetElement(esize, result, second, - ir.FPMulAdd(operand3_elem2, element4, element3, true)); + result = ir.VectorSetElement(esize, result, first, ir.FPMulAdd(operand3_elem1, element2, element1)); + result = ir.VectorSetElement(esize, result, second, ir.FPMulAdd(operand3_elem2, element4, element3)); } ir.SetQ(Vd, result); @@ -166,10 +164,8 @@ bool TranslatorVisitor::FCADD_vec(bool Q, Imm<2> size, Vec Vm, Imm<1> rot, Vec V const IR::U32U64 operand1_elem1 = ir.VectorGetElement(esize, operand1, first); const IR::U32U64 operand1_elem3 = ir.VectorGetElement(esize, operand1, second); - result = ir.VectorSetElement(esize, result, first, - ir.FPAdd(operand1_elem1, element1, true)); - result = ir.VectorSetElement(esize, result, second, - ir.FPAdd(operand1_elem3, element3, true)); + result = ir.VectorSetElement(esize, result, first, ir.FPAdd(operand1_elem1, element1)); + result = ir.VectorSetElement(esize, result, second, ir.FPAdd(operand1_elem3, element3)); } ir.SetQ(Vd, result); diff --git a/src/frontend/A64/translate/impl/simd_vector_x_indexed_element.cpp b/src/frontend/A64/translate/impl/simd_vector_x_indexed_element.cpp index 90d49607..7862545d 100644 --- a/src/frontend/A64/translate/impl/simd_vector_x_indexed_element.cpp +++ b/src/frontend/A64/translate/impl/simd_vector_x_indexed_element.cpp @@ -296,10 +296,8 @@ bool TranslatorVisitor::FCMLA_elt(bool Q, Imm<2> size, Imm<1> L, Imm<1> M, Imm<4 const IR::U32U64 operand3_elem1 = ir.VectorGetElement(esize, operand3, first); const IR::U32U64 operand3_elem2 = ir.VectorGetElement(esize, operand3, second); - result = ir.VectorSetElement(esize, result, first, - ir.FPMulAdd(operand3_elem1, element2, element1, true)); - result = ir.VectorSetElement(esize, result, second, - ir.FPMulAdd(operand3_elem2, element4, element3, true)); + result = ir.VectorSetElement(esize, result, first, ir.FPMulAdd(operand3_elem1, element2, element1)); + result = ir.VectorSetElement(esize, result, second, ir.FPMulAdd(operand3_elem2, element4, element3)); } ir.SetQ(Vd, result); diff --git a/src/frontend/ir/ir_emitter.h b/src/frontend/ir/ir_emitter.h index 16403cf2..eac96060 100644 --- a/src/frontend/ir/ir_emitter.h +++ b/src/frontend/ir/ir_emitter.h @@ -310,15 +310,15 @@ public: U128 ZeroVector(); U16U32U64 FPAbs(const U16U32U64& a); - U32U64 FPAdd(const U32U64& a, const U32U64& b, bool fpcr_controlled); - NZCV FPCompare(const U32U64& a, const U32U64& b, bool exc_on_qnan, bool fpcr_controlled); - U32U64 FPDiv(const U32U64& a, const U32U64& b, bool fpcr_controlled); - U32U64 FPMax(const U32U64& a, const U32U64& b, bool fpcr_controlled); - U32U64 FPMaxNumeric(const U32U64& a, const U32U64& b, bool fpcr_controlled); - U32U64 FPMin(const U32U64& a, const U32U64& b, bool fpcr_controlled); - U32U64 FPMinNumeric(const U32U64& a, const U32U64& b, bool fpcr_controlled); - U32U64 FPMul(const U32U64& a, const U32U64& b, bool fpcr_controlled); - U16U32U64 FPMulAdd(const U16U32U64& addend, const U16U32U64& op1, const U16U32U64& op2, bool fpcr_controlled); + U32U64 FPAdd(const U32U64& a, const U32U64& b, bool fpcr_controlled = true); + NZCV FPCompare(const U32U64& a, const U32U64& b, bool exc_on_qnan, bool fpcr_controlled = true); + U32U64 FPDiv(const U32U64& a, const U32U64& b, bool fpcr_controlled = true); + U32U64 FPMax(const U32U64& a, const U32U64& b, bool fpcr_controlled = true); + U32U64 FPMaxNumeric(const U32U64& a, const U32U64& b, bool fpcr_controlled = true); + U32U64 FPMin(const U32U64& a, const U32U64& b, bool fpcr_controlled = true); + U32U64 FPMinNumeric(const U32U64& a, const U32U64& b, bool fpcr_controlled = true); + U32U64 FPMul(const U32U64& a, const U32U64& b, bool fpcr_controlled = true); + U16U32U64 FPMulAdd(const U16U32U64& addend, const U16U32U64& op1, const U16U32U64& op2, bool fpcr_controlled = true); U32U64 FPMulX(const U32U64& a, const U32U64& b); U16U32U64 FPNeg(const U16U32U64& a); U16U32U64 FPRecipEstimate(const U16U32U64& a); @@ -328,7 +328,7 @@ public: U16U32U64 FPRSqrtEstimate(const U16U32U64& a); U16U32U64 FPRSqrtStepFused(const U16U32U64& a, const U16U32U64& b); U32U64 FPSqrt(const U32U64& a); - U32U64 FPSub(const U32U64& a, const U32U64& b, bool fpcr_controlled); + U32U64 FPSub(const U32U64& a, const U32U64& b, bool fpcr_controlled = true); U16 FPDoubleToHalf(const U64& a, FP::RoundingMode rounding); U32 FPDoubleToSingle(const U64& a, FP::RoundingMode rounding); U64 FPHalfToDouble(const U16& a, FP::RoundingMode rounding);