From d5af052f0659ea3666827dbd7ea7441aa2a2cc57 Mon Sep 17 00:00:00 2001 From: MerryMage Date: Tue, 13 Feb 2018 18:29:54 +0000 Subject: [PATCH] A64: Implement CMGE (register) --- src/frontend/A64/decoder/a64.inc | 2 +- src/frontend/A64/translate/impl/simd_three_same.cpp | 12 ++++++++++++ 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc index 1a382d81..96f03172 100644 --- a/src/frontend/A64/decoder/a64.inc +++ b/src/frontend/A64/decoder/a64.inc @@ -708,7 +708,7 @@ INST(NOT, "NOT", "0Q101 //INST(SHSUB, "SHSUB", "0Q001110zz1mmmmm001001nnnnnddddd") //INST(SQSUB_2, "SQSUB", "0Q001110zz1mmmmm001011nnnnnddddd") INST(CMGT_reg_2, "CMGT (register)", "0Q001110zz1mmmmm001101nnnnnddddd") -//INST(CMGE_reg_2, "CMGE (register)", "0Q001110zz1mmmmm001111nnnnnddddd") +INST(CMGE_reg_2, "CMGE (register)", "0Q001110zz1mmmmm001111nnnnnddddd") //INST(SSHL_2, "SSHL", "0Q001110zz1mmmmm010001nnnnnddddd") //INST(SQSHL_reg_2, "SQSHL (register)", "0Q001110zz1mmmmm010011nnnnnddddd") //INST(SRSHL_2, "SRSHL", "0Q001110zz1mmmmm010101nnnnnddddd") diff --git a/src/frontend/A64/translate/impl/simd_three_same.cpp b/src/frontend/A64/translate/impl/simd_three_same.cpp index 1a19b4ad..db022413 100644 --- a/src/frontend/A64/translate/impl/simd_three_same.cpp +++ b/src/frontend/A64/translate/impl/simd_three_same.cpp @@ -20,6 +20,18 @@ bool TranslatorVisitor::CMGT_reg_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) return true; } +bool TranslatorVisitor::CMGE_reg_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { + if (size == 0b11 && !Q) return ReservedValue(); + const size_t esize = 8 << size.ZeroExtend(); + const size_t datasize = Q ? 128 : 64; + + const IR::U128 operand1 = V(datasize, Vn); + const IR::U128 operand2 = V(datasize, Vm); + const IR::U128 result = ir.VectorGreaterEqualSigned(esize, operand1, operand2); + V(datasize, Vd, result); + return true; +} + bool TranslatorVisitor::SMAX(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { if (size == 0b11) { return ReservedValue();