diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc index 8013a2a6..19b4e123 100644 --- a/src/frontend/A64/decoder/a64.inc +++ b/src/frontend/A64/decoder/a64.inc @@ -639,7 +639,7 @@ INST(NEG_2, "NEG (vector)", "0Q101 //INST(UCVTF_int_4, "UCVTF (vector, integer)", "0Q1011100z100001110110nnnnnddddd") INST(NOT, "NOT", "0Q10111000100000010110nnnnnddddd") INST(RBIT_asimd, "RBIT (vector)", "0Q10111001100000010110nnnnnddddd") -//INST(FNEG_1, "FNEG (vector)", "0Q10111011111000111110nnnnnddddd") +INST(FNEG_1, "FNEG (vector)", "0Q10111011111000111110nnnnnddddd") INST(FNEG_2, "FNEG (vector)", "0Q1011101z100000111110nnnnnddddd") //INST(FRINTI_1, "FRINTI (vector)", "0Q10111011111001100110nnnnnddddd") //INST(FRINTI_2, "FRINTI (vector)", "0Q1011101z100001100110nnnnnddddd") diff --git a/src/frontend/A64/translate/impl/simd_two_register_misc.cpp b/src/frontend/A64/translate/impl/simd_two_register_misc.cpp index ec329a1d..f5f03b89 100644 --- a/src/frontend/A64/translate/impl/simd_two_register_misc.cpp +++ b/src/frontend/A64/translate/impl/simd_two_register_misc.cpp @@ -114,6 +114,17 @@ bool TranslatorVisitor::XTN(bool Q, Imm<2> size, Vec Vn, Vec Vd) { return true; } +bool TranslatorVisitor::FNEG_1(bool Q, Vec Vn, Vec Vd) { + const size_t datasize = Q ? 128 : 64; + + const IR::U128 operand = V(datasize, Vn); + const IR::U128 mask = ir.VectorBroadcast(64, I(64, 0x8000800080008000)); + const IR::U128 result = ir.VectorEor(operand, mask); + + V(datasize, Vd, result); + return true; +} + bool TranslatorVisitor::FNEG_2(bool Q, bool sz, Vec Vn, Vec Vd) { if (sz && !Q) { return ReservedValue();