From e009d9992401d49b12a2927854a6c3bda9f7ff5f Mon Sep 17 00:00:00 2001 From: MerryMage Date: Sun, 21 Jun 2020 17:09:56 +0100 Subject: [PATCH] A32: Implement ASIMD VSHRN --- src/frontend/A32/decoder/asimd.inc | 2 +- .../translate/impl/asimd_two_regs_shift.cpp | 22 +++++++++++++++++++ .../A32/translate/impl/translate_arm.h | 3 ++- 3 files changed, 25 insertions(+), 2 deletions(-) diff --git a/src/frontend/A32/decoder/asimd.inc b/src/frontend/A32/decoder/asimd.inc index 7f38100b..be01a865 100644 --- a/src/frontend/A32/decoder/asimd.inc +++ b/src/frontend/A32/decoder/asimd.inc @@ -71,7 +71,7 @@ INST(asimd_VSRI, "VSRI", "111100111Diiiiiidddd010 INST(asimd_VSHL, "VSHL", "111100101Diiiiiidddd0101LQM1mmmm") // ASIMD INST(asimd_VSLI, "VSLI", "111100111Diiiiiidddd0101LQM1mmmm") // ASIMD //INST(asimd_VQSHL, "VQSHL" , "1111001U1-vvv-------011xLB-1----") // ASIMD -//INST(asimd_VSHRN, "VSHRN", "111100101-vvv-------100000-1----") // ASIMD +INST(asimd_VSHRN, "VSHRN", "111100101Diiiiiidddd100000M1mmmm") // ASIMD //INST(asimd_VRSHRN, "VRSHRN", "111100101-vvv-------100001-1----") // ASIMD //INST(asimd_VQSHRUN, "VQSHRUN", "111100111-vvv-------100000-1----") // ASIMD //INST(asimd_VQRSHRUN, "VQRSHRUN", "111100111-vvv-------100001-1----") // ASIMD diff --git a/src/frontend/A32/translate/impl/asimd_two_regs_shift.cpp b/src/frontend/A32/translate/impl/asimd_two_regs_shift.cpp index a6ed0be9..da9ff386 100644 --- a/src/frontend/A32/translate/impl/asimd_two_regs_shift.cpp +++ b/src/frontend/A32/translate/impl/asimd_two_regs_shift.cpp @@ -175,4 +175,26 @@ bool ArmTranslatorVisitor::asimd_VSHL(bool D, size_t imm6, size_t Vd, bool L, bo return true; } +bool ArmTranslatorVisitor::asimd_VSHRN(bool D, size_t imm6, size_t Vd, bool M, size_t Vm) { + if (Common::Bits<3, 5>(imm6) == 0) { + // TODO: Decode error + return UndefinedInstruction(); + } + + if (Common::Bit<0>(Vm)) { + return UndefinedInstruction(); + } + + const auto [esize, shift_amount] = ElementSizeAndShiftAmount(true, false, imm6); + const auto d = ToVector(false, Vd, D); + const auto m = ToVector(true, Vm, M); + + const auto reg_m = ir.GetVector(m); + const auto wide_result = ir.VectorLogicalShiftRight(2 * esize, reg_m, shift_amount); + const auto result = ir.VectorNarrow(2 * esize, wide_result); + + ir.SetVector(d, result); + return true; +} + } // namespace Dynarmic::A32 diff --git a/src/frontend/A32/translate/impl/translate_arm.h b/src/frontend/A32/translate/impl/translate_arm.h index 6b194689..3dbf296c 100644 --- a/src/frontend/A32/translate/impl/translate_arm.h +++ b/src/frontend/A32/translate/impl/translate_arm.h @@ -506,8 +506,9 @@ struct ArmTranslatorVisitor final { bool asimd_VRSHR(bool U, bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm); bool asimd_VRSRA(bool U, bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm); bool asimd_VSRI(bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm); - bool asimd_VSLI(bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm); bool asimd_VSHL(bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm); + bool asimd_VSLI(bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm); + bool asimd_VSHRN(bool D, size_t imm6, size_t Vd, bool M, size_t Vm); // Advanced SIMD two register, miscellaneous bool asimd_VREV(bool D, size_t sz, size_t Vd, size_t op, bool Q, bool M, size_t Vm);