diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt index ebf74a25..bb64ca41 100644 --- a/src/CMakeLists.txt +++ b/src/CMakeLists.txt @@ -51,6 +51,15 @@ add_library(dynarmic frontend/A32/translate/translate_thumb.cpp frontend/A32/types.cpp frontend/A32/types.h + frontend/A64/decoder/a64.h + frontend/A64/imm.h + frontend/A64/location_descriptor.cpp + frontend/A64/location_descriptor.h + frontend/A64/translate/impl/impl.h + frontend/A64/translate/translate.cpp + frontend/A64/translate/translate.h + frontend/A64/types.cpp + frontend/A64/types.h frontend/decoder/decoder_detail.h frontend/decoder/matcher.h frontend/ir/basic_block.cpp diff --git a/src/frontend/A64/FPCR.h b/src/frontend/A64/FPCR.h new file mode 100644 index 00000000..d2a17c9a --- /dev/null +++ b/src/frontend/A64/FPCR.h @@ -0,0 +1,112 @@ +/* This file is part of the dynarmic project. + * Copyright (c) 2016 MerryMage + * This software may be used and distributed according to the terms of the GNU + * General Public License version 2 or any later version. + */ + +#pragma once + +#include + +#include "common/bit_util.h" +#include "common/common_types.h" + +namespace Dynarmic { +namespace A64 { + +/** + * Representation of the Floating-Point Control Register. + */ +class FPCR final +{ +public: + enum class RoundingMode { + ToNearest, + TowardsPlusInfinity, + TowardsMinusInfinity, + TowardsZero + }; + + FPCR() = default; + FPCR(const FPCR&) = default; + FPCR(FPCR&&) = default; + explicit FPCR(u32 data) : value{data & mask} {} + + FPCR& operator=(const FPCR&) = default; + FPCR& operator=(FPCR&&) = default; + FPCR& operator=(u32 data) { + value = data & mask; + return *this; + } + + /// Alternate half-precision control flag. + bool AHP() const { + return Common::Bit<26>(value); + } + + /// Default NaN mode control bit. + bool DN() const { + return Common::Bit<25>(value); + } + + /// Flush-to-zero mode control bit. + bool FZ() const { + return Common::Bit<24>(value); + } + + /// Rounding mode control field. + RoundingMode RMode() const { + return static_cast(Common::Bits<22, 23>(value)); + } + + /// Input denormal exception trap enable flag. + bool IDE() const { + return Common::Bit<15>(value); + } + + /// Inexact exception trap enable flag. + bool IXE() const { + return Common::Bit<12>(value); + } + + /// Underflow exception trap enable flag. + bool UFE() const { + return Common::Bit<11>(value); + } + + /// Overflow exception trap enable flag. + bool OFE() const { + return Common::Bit<10>(value); + } + + /// Division by zero exception trap enable flag. + bool DZE() const { + return Common::Bit<9>(value); + } + + /// Invalid operation exception trap enable flag. + bool IOE() const { + return Common::Bit<8>(value); + } + + /// Gets the underlying raw value within the FPCR. + u32 Value() const { + return value; + } + +private: + // Bits 0-7, 13-14, 19, and 27-31 are reserved. + static constexpr u32 mask = 0x07F79F00; + u32 value = 0; +}; + +inline bool operator==(FPCR lhs, FPCR rhs) { + return lhs.Value() == rhs.Value(); +} + +inline bool operator!=(FPCR lhs, FPCR rhs) { + return !operator==(lhs, rhs); +} + +} // namespace A64 +} // namespace Dynarmic diff --git a/src/frontend/A64/decoder/a64.h b/src/frontend/A64/decoder/a64.h new file mode 100644 index 00000000..6a0f6325 --- /dev/null +++ b/src/frontend/A64/decoder/a64.h @@ -0,0 +1,1069 @@ +/* This file is part of the dynarmic project. + * Copyright (c) 2018 MerryMage + * This software may be used and distributed according to the terms of the GNU + * General Public License version 2 or any later version. + */ + +#pragma once + +#include +#include +#include + +#include + +#include "common/bit_util.h" +#include "common/common_types.h" +#include "frontend/decoder/decoder_detail.h" +#include "frontend/decoder/matcher.h" + +namespace Dynarmic { +namespace A64 { + +template +using Matcher = Decoder::Matcher; + +template +std::vector> GetDecodeTable() { + std::vector> table = { + +#define INST(fn, name, bitstring) Decoder::detail::detail>::GetMatcher(fn, name, bitstring) + + // Data processing - Immediate - PC relative addressing + //INST(&V::ADR, "ADR", "0ii10000iiiiiiiiiiiiiiiiiiiddddd"), + //INST(&V::ADRP, "ADRP", "1ii10000iiiiiiiiiiiiiiiiiiiddddd"), + + // Data processing - Immediate - Add/Sub + //INST(&V::ADD_imm, "ADD (immediate)", "z0010001ssiiiiiiiiiiiinnnnnddddd"), + //INST(&V::ADDS_imm, "ADDS (immediate)", "z0110001ssiiiiiiiiiiiinnnnnddddd"), + //INST(&V::SUB_imm, "SUB (immediate)", "z1010001ssiiiiiiiiiiiinnnnnddddd"), + //INST(&V::SUBS_imm, "SUBS (immediate)", "z1110001ssiiiiiiiiiiiinnnnnddddd"), + + // Data processing - Immediate - Logical + //INST(&V::AND_imm, "AND (immediate)", "z00100100Nrrrrrrssssssnnnnnddddd"), + //INST(&V::ORR_imm, "ORR (immediate)", "z01100100Nrrrrrrssssssnnnnnddddd"), + //INST(&V::EOR_imm, "EOR (immediate)", "z10100100Nrrrrrrssssssnnnnnddddd"), + //INST(&V::ANDS_imm, "ANDS (immediate)", "z11100100Nrrrrrrssssssnnnnnddddd"), + + // Data processing - Immediate - Move Wide + //INST(&V::MOVN, "MOVN", "z00100101ssiiiiiiiiiiiiiiiiddddd"), + //INST(&V::MOVZ, "MOVZ", "z10100101ssiiiiiiiiiiiiiiiiddddd"), + //INST(&V::MOVK, "MOVK", "z11100101ssiiiiiiiiiiiiiiiiddddd"), + + // Data processing - Immediate - Bitfield + //INST(&V::SBFM, "SBFM", "z00100110Nrrrrrrssssssnnnnnddddd"), + //INST(&V::BFM, "BFM", "z01100110Nrrrrrrssssssnnnnnddddd"), + //INST(&V::UBFM, "UBFM", "z10100110Nrrrrrrssssssnnnnnddddd"), + + // Data processing - Immediate - Extract + //INST(&V::EXTR, "EXTR", "z00100111N0mmmmmssssssnnnnnddddd"), + + // Conditional branch + //INST(&V::B_cond, "B.cond", "01010100iiiiiiiiiiiiiiiiiii0cccc"), + + // Exception generation + //INST(&V::SVC, "SVC", "11010100000iiiiiiiiiiiiiiii00001"), + //INST(&V::HVC, "HVC", "11010100000iiiiiiiiiiiiiiii00010"), + //INST(&V::SMC, "SMC", "11010100000iiiiiiiiiiiiiiii00011"), + //INST(&V::BRK, "BRK", "11010100001iiiiiiiiiiiiiiii00000"), + //INST(&V::HLT, "HLT", "11010100010iiiiiiiiiiiiiiii00000"), + //INST(&V::DCPS1, "DCPS1", "11010100101iiiiiiiiiiiiiiii00001"), + //INST(&V::DCPS2, "DCPS2", "11010100101iiiiiiiiiiiiiiii00010"), + //INST(&V::DCPS3, "DCPS3", "11010100101iiiiiiiiiiiiiiii00011"), + + // System + //INST(&V::MSR_imm, "MSR (immediate)", "1101010100000ooo0100MMMMooo11111"), + //INST(&V::HINT, "HINT", "11010101000000110010MMMMooo11111"), + //INST(&V::NOP, "NOP", "11010101000000110010000000011111"), + //INST(&V::YIELD, "YIELD", "11010101000000110010000000111111"), + //INST(&V::WFE, "WFE", "11010101000000110010000001011111"), + //INST(&V::WFI, "WFI", "11010101000000110010000001111111"), + //INST(&V::SEV, "SEV", "11010101000000110010000010011111"), + //INST(&V::SEVL, "SEVL", "11010101000000110010000010111111"), + //INST(&V::XPAC_1, "XPACD, XPACI, XPACLRI", "110110101100000101000D11111ddddd"), + //INST(&V::XPAC_2, "XPACD, XPACI, XPACLRI", "11010101000000110010000011111111"), + //INST(&V::PACIA_1, "PACIA, PACIA1716, PACIASP, PACIAZ, PACIZA", "110110101100000100Z000nnnnnddddd"), + //INST(&V::PACIA_2, "PACIA, PACIA1716, PACIASP, PACIAZ, PACIZA", "1101010100000011001000-100-11111"), + //INST(&V::PACIB_1, "PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZB", "110110101100000100Z001nnnnnddddd"), + //INST(&V::PACIB_2, "PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZB", "1101010100000011001000-101-11111"), + //INST(&V::AUTIA_1, "AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZA", "110110101100000100Z100nnnnnddddd"), + //INST(&V::AUTIA_2, "AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZA", "1101010100000011001000-110-11111"), + //INST(&V::AUTIB_1, "AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZB", "110110101100000100Z101nnnnnddddd"), + //INST(&V::AUTIB_2, "AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZB", "1101010100000011001000-111-11111"), + //INST(&V::ESB, "ESB", "11010101000000110010001000011111"), + //INST(&V::PSB, "PSB CSYNC", "11010101000000110010001000111111"), + //INST(&V::CLREX, "CLREX", "11010101000000110011MMMM01011111"), + //INST(&V::DSB, "DSB", "11010101000000110011MMMM10011111"), + //INST(&V::DMB, "DMB", "11010101000000110011MMMM10111111"), + //INST(&V::ISB, "ISB", "11010101000000110011MMMM11011111"), + //INST(&V::SYS, "SYS", "1101010100001oooNNNNMMMMooottttt"), + //INST(&V::MSR_reg, "MSR (register)", "110101010001poooNNNNMMMMooottttt"), + //INST(&V::SYSL, "SYSL", "1101010100101oooNNNNMMMMooottttt"), + //INST(&V::MRS, "MRS", "110101010011poooNNNNMMMMooottttt"), + + // Unconditonal branch (Register) + //INST(&V::BR, "BR", "1101011000011111000000nnnnn00000"), + //INST(&V::BRA, "BRAA, BRAAZ, BRAB, BRABZ", "1101011Z0001111100001Mnnnnnmmmmm"), + //INST(&V::BLR, "BLR", "1101011000111111000000nnnnn00000"), + //INST(&V::BLRA, "BLRAA, BLRAAZ, BLRAB, BLRABZ", "1101011Z0011111100001Mnnnnnmmmmm"), + //INST(&V::RET, "RET", "1101011001011111000000nnnnn00000"), + //INST(&V::RETA, "RETAA, RETAB", "110101100101111100001M1111111111"), + //INST(&V::ERET, "ERET", "11010110100111110000001111100000"), + //INST(&V::ERETA, "ERETAA, ERETAB", "110101101001111100001M1111111111"), + //INST(&V::DRPS, "DRPS", "11010110101111110000001111100000"), + + // Unconditonal branch (immediate) + //INST(&V::B_uncond, "B", "000101iiiiiiiiiiiiiiiiiiiiiiiiii"), + //INST(&V::BL, "BL", "100101iiiiiiiiiiiiiiiiiiiiiiiiii"), + + // Compare and branch (immediate) + //INST(&V::CBZ, "CBZ", "z0110100iiiiiiiiiiiiiiiiiiittttt"), + //INST(&V::CBNZ, "CBNZ", "z0110101iiiiiiiiiiiiiiiiiiittttt"), + //INST(&V::TBZ, "TBZ", "b0110110bbbbbiiiiiiiiiiiiiittttt"), + //INST(&V::TBNZ, "TBNZ", "b0110111bbbbbiiiiiiiiiiiiiittttt"), + + // Loads and stores - Advanced SIMD Load/Store multiple structures + //INST(&V::ST4_mult_1, "ST4 (multiple structures)", "0Q001100000000000000zznnnnnttttt"), + //INST(&V::ST4_mult_2, "ST4 (multiple structures)", "0Q001100100mmmmm0000zznnnnnttttt"), + //INST(&V::ST1_mult_1, "ST1 (multiple structures)", "0Q00110000000000--1-zznnnnnttttt"), + //INST(&V::ST1_mult_2, "ST1 (multiple structures)", "0Q001100100mmmmm--1-zznnnnnttttt"), + //INST(&V::ST3_mult_1, "ST3 (multiple structures)", "0Q001100000000000100zznnnnnttttt"), + //INST(&V::ST3_mult_2, "ST3 (multiple structures)", "0Q001100100mmmmm0100zznnnnnttttt"), + //INST(&V::ST2_mult_1, "ST2 (multiple structures)", "0Q001100000000001000zznnnnnttttt"), + //INST(&V::ST2_mult_2, "ST2 (multiple structures)", "0Q001100100mmmmm1000zznnnnnttttt"), + //INST(&V::LD4_mult_1, "LD4 (multiple structures)", "0Q001100010000000000zznnnnnttttt"), + //INST(&V::LD4_mult_2, "LD4 (multiple structures)", "0Q001100110mmmmm0000zznnnnnttttt"), + //INST(&V::LD1_mult_1, "LD1 (multiple structures)", "0Q00110001000000--1-zznnnnnttttt"), + //INST(&V::LD1_mult_2, "LD1 (multiple structures)", "0Q001100110mmmmm--1-zznnnnnttttt"), + //INST(&V::LD3_mult_1, "LD3 (multiple structures)", "0Q001100010000000100zznnnnnttttt"), + //INST(&V::LD3_mult_2, "LD3 (multiple structures)", "0Q001100110mmmmm0100zznnnnnttttt"), + //INST(&V::LD2_mult_1, "LD2 (multiple structures)", "0Q001100010000001000zznnnnnttttt"), + //INST(&V::LD2_mult_2, "LD2 (multiple structures)", "0Q001100110mmmmm1000zznnnnnttttt"), + + // Loads and stores - Advanced SIMD Load/Store single structures + //INST(&V::ST1_sngl_1, "ST1 (single structure)", "0Q00110100000000--0Szznnnnnttttt"), + //INST(&V::ST1_sngl_2, "ST1 (single structure)", "0Q001101100mmmmm--0Szznnnnnttttt"), + //INST(&V::ST3_sngl_1, "ST3 (single structure)", "0Q00110100000000--1Szznnnnnttttt"), + //INST(&V::ST3_sngl_2, "ST3 (single structure)", "0Q001101100mmmmm--1Szznnnnnttttt"), + //INST(&V::ST2_sngl_1, "ST2 (single structure)", "0Q00110100100000--0Szznnnnnttttt"), + //INST(&V::ST2_sngl_2, "ST2 (single structure)", "0Q001101101mmmmm--0Szznnnnnttttt"), + //INST(&V::ST4_sngl_1, "ST4 (single structure)", "0Q00110100100000--1Szznnnnnttttt"), + //INST(&V::ST4_sngl_2, "ST4 (single structure)", "0Q001101101mmmmm--1Szznnnnnttttt"), + //INST(&V::LD1_sngl_1, "LD1 (single structure)", "0Q00110101000000--0Szznnnnnttttt"), + //INST(&V::LD1_sngl_2, "LD1 (single structure)", "0Q001101110mmmmm--0Szznnnnnttttt"), + //INST(&V::LD3_sngl_1, "LD3 (single structure)", "0Q00110101000000--1Szznnnnnttttt"), + //INST(&V::LD3_sngl_2, "LD3 (single structure)", "0Q001101110mmmmm--1Szznnnnnttttt"), + //INST(&V::LD1R_1, "LD1R", "0Q001101010000001100zznnnnnttttt"), + //INST(&V::LD1R_2, "LD1R", "0Q001101110mmmmm1100zznnnnnttttt"), + //INST(&V::LD3R_1, "LD3R", "0Q001101010000001110zznnnnnttttt"), + //INST(&V::LD3R_2, "LD3R", "0Q001101110mmmmm1110zznnnnnttttt"), + //INST(&V::LD2_sngl_1, "LD2 (single structure)", "0Q00110101100000--0Szznnnnnttttt"), + //INST(&V::LD2_sngl_2, "LD2 (single structure)", "0Q001101111mmmmm--0Szznnnnnttttt"), + //INST(&V::LD4_sngl_1, "LD4 (single structure)", "0Q00110101100000--1Szznnnnnttttt"), + //INST(&V::LD4_sngl_2, "LD4 (single structure)", "0Q001101111mmmmm--1Szznnnnnttttt"), + //INST(&V::LD2R_1, "LD2R", "0Q001101011000001100zznnnnnttttt"), + //INST(&V::LD2R_2, "LD2R", "0Q001101111mmmmm1100zznnnnnttttt"), + //INST(&V::LD4R_1, "LD4R", "0Q001101011000001110zznnnnnttttt"), + //INST(&V::LD4R_2, "LD4R", "0Q001101111mmmmm1110zznnnnnttttt"), + + // Loads and stores - Load/Store Exclusive + //INST(&V::STXRB, "STXRB", "00001000000sssss011111nnnnnttttt"), + //INST(&V::STLXRB, "STLXRB", "00001000000sssss111111nnnnnttttt"), + //INST(&V::CASP, "CASP, CASPA, CASPAL, CASPL", "0z0010000L1sssssp11111nnnnnttttt"), + //INST(&V::LDXRB, "LDXRB", "0000100001011111011111nnnnnttttt"), + //INST(&V::LDAXRB, "LDAXRB", "0000100001011111111111nnnnnttttt"), + //INST(&V::STLLRB, "STLLRB", "0000100010011111011111nnnnnttttt"), + //INST(&V::STLRB, "STLRB", "0000100010011111111111nnnnnttttt"), + //INST(&V::CASB, "CASB, CASAB, CASALB, CASLB", "000010001L1sssssp11111nnnnnttttt"), + //INST(&V::LDLARB, "LDLARB", "0000100011011111011111nnnnnttttt"), + //INST(&V::LDARB, "LDARB", "0000100011011111111111nnnnnttttt"), + //INST(&V::STXRH, "STXRH", "01001000000sssss011111nnnnnttttt"), + //INST(&V::STLXRH, "STLXRH", "01001000000sssss111111nnnnnttttt"), + //INST(&V::LDXRH, "LDXRH", "0100100001011111011111nnnnnttttt"), + //INST(&V::LDAXRH, "LDAXRH", "0100100001011111111111nnnnnttttt"), + //INST(&V::STLLRH, "STLLRH", "0100100010011111011111nnnnnttttt"), + //INST(&V::STLRH, "STLRH", "0100100010011111111111nnnnnttttt"), + //INST(&V::CASH, "CASH, CASAH, CASALH, CASLH", "010010001L1sssssp11111nnnnnttttt"), + //INST(&V::LDLARH, "LDLARH", "0100100011011111011111nnnnnttttt"), + //INST(&V::LDARH, "LDARH", "0100100011011111111111nnnnnttttt"), + //INST(&V::STXR, "STXR", "1-001000000sssss011111nnnnnttttt"), + //INST(&V::STLXR, "STLXR", "1-001000000sssss111111nnnnnttttt"), + //INST(&V::STXP, "STXP", "1z001000001sssss0uuuuunnnnnttttt"), + //INST(&V::STLXP, "STLXP", "1z001000001sssss1uuuuunnnnnttttt"), + //INST(&V::LDXR, "LDXR", "1-00100001011111011111nnnnnttttt"), + //INST(&V::LDAXR, "LDAXR", "1-00100001011111111111nnnnnttttt"), + //INST(&V::LDXP, "LDXP", "1z001000011111110uuuuunnnnnttttt"), + //INST(&V::LDAXP, "LDAXP", "1z001000011111111uuuuunnnnnttttt"), + //INST(&V::STLLR, "STLLR", "1-00100010011111011111nnnnnttttt"), + //INST(&V::STLR, "STLR", "1-00100010011111111111nnnnnttttt"), + //INST(&V::CAS, "CAS, CASA, CASAL, CASL", "1-0010001L1sssssp11111nnnnnttttt"), + //INST(&V::LDLAR, "LDLAR", "1-00100011011111011111nnnnnttttt"), + //INST(&V::LDAR, "LDAR", "1-00100011011111111111nnnnnttttt"), + + // Loads and stores - Load register (literal) + //INST(&V::LDR_lit_gen, "LDR (literal)", "0-011000iiiiiiiiiiiiiiiiiiittttt"), + //INST(&V::LDR_lit_fpsimd, "LDR (literal, SIMD&FP)", "oo011100iiiiiiiiiiiiiiiiiiittttt"), + //INST(&V::LDRSW_lit, "LDRSW (literal)", "10011000iiiiiiiiiiiiiiiiiiittttt"), + //INST(&V::PRFM_lit, "PRFM (literal)", "11011000iiiiiiiiiiiiiiiiiiittttt"), + + // Loads and stores - Load/Store no-allocate pair + //INST(&V::STNP_gen, "STNP", "-010100000iiiiiiiuuuuunnnnnttttt"), + //INST(&V::LDNP_gen, "LDNP", "-010100001iiiiiiiuuuuunnnnnttttt"), + //INST(&V::STNP_fpsimd, "STNP (SIMD&FP)", "oo10110000iiiiiiiuuuuunnnnnttttt"), + //INST(&V::LDNP_fpsimd, "LDNP (SIMD&FP)", "oo10110001iiiiiiiuuuuunnnnnttttt"), + + // Loads and stores - Load/Store register pair + //INST(&V::STP_gen_1, "STP", "-010100010iiiiiiiuuuuunnnnnttttt"), + //INST(&V::STP_gen_2, "STP", "-010100110iiiiiiiuuuuunnnnnttttt"), + //INST(&V::STP_gen_3, "STP", "-010100100iiiiiiiuuuuunnnnnttttt"), + //INST(&V::LDP_gen_1, "LDP", "-010100011iiiiiiiuuuuunnnnnttttt"), + //INST(&V::LDP_gen_2, "LDP", "-010100111iiiiiiiuuuuunnnnnttttt"), + //INST(&V::LDP_gen_3, "LDP", "-010100101iiiiiiiuuuuunnnnnttttt"), + //INST(&V::STP_fpsimd_1, "STP (SIMD&FP)", "oo10110010iiiiiiiuuuuunnnnnttttt"), + //INST(&V::STP_fpsimd_2, "STP (SIMD&FP)", "oo10110110iiiiiiiuuuuunnnnnttttt"), + //INST(&V::STP_fpsimd_3, "STP (SIMD&FP)", "oo10110100iiiiiiiuuuuunnnnnttttt"), + //INST(&V::LDP_fpsimd_1, "LDP (SIMD&FP)", "oo10110011iiiiiiiuuuuunnnnnttttt"), + //INST(&V::LDP_fpsimd_2, "LDP (SIMD&FP)", "oo10110111iiiiiiiuuuuunnnnnttttt"), + //INST(&V::LDP_fpsimd_3, "LDP (SIMD&FP)", "oo10110101iiiiiiiuuuuunnnnnttttt"), + //INST(&V::LDPSW_1, "LDPSW", "0110100011iiiiiiiuuuuunnnnnttttt"), + //INST(&V::LDPSW_2, "LDPSW", "0110100111iiiiiiiuuuuunnnnnttttt"), + //INST(&V::LDPSW_3, "LDPSW", "0110100101iiiiiiiuuuuunnnnnttttt"), + + // Loads and stores - Load/Store register (unscaled immediate) + //INST(&V::STURB, "STURB", "00111000000iiiiiiiii00nnnnnttttt"), + //INST(&V::LDURB, "LDURB", "00111000010iiiiiiiii00nnnnnttttt"), + //INST(&V::LDURSB, "LDURSB", "001110001-0iiiiiiiii00nnnnnttttt"), + //INST(&V::STUR_fpsimd, "STUR (SIMD&FP)", "zz111100-00iiiiiiiii00nnnnnttttt"), + //INST(&V::LDUR_fpsimd, "LDUR (SIMD&FP)", "zz111100-10iiiiiiiii00nnnnnttttt"), + //INST(&V::STURH, "STURH", "01111000000iiiiiiiii00nnnnnttttt"), + //INST(&V::LDURH, "LDURH", "01111000010iiiiiiiii00nnnnnttttt"), + //INST(&V::LDURSH, "LDURSH", "011110001-0iiiiiiiii00nnnnnttttt"), + //INST(&V::STUR_gen, "STUR", "1-111000000iiiiiiiii00nnnnnttttt"), + //INST(&V::LDUR_gen, "LDUR", "1-111000010iiiiiiiii00nnnnnttttt"), + //INST(&V::LDURSW, "LDURSW", "10111000100iiiiiiiii00nnnnnttttt"), + //INST(&V::PRFUM, "PRFM (unscaled offset)", "11111000100iiiiiiiii00nnnnnttttt"), + //INST(&V::PRFM_imm, "PRFM (immediate)", "1111100110iiiiiiiiiiiinnnnnttttt"), + + // Loads and stores - Load/Store register (immediate pre/post-indexed) + //INST(&V::STRB_imm_1, "STRB (immediate)", "00111000000iiiiiiiii01nnnnnttttt"), + //INST(&V::STRB_imm_2, "STRB (immediate)", "00111000000iiiiiiiii11nnnnnttttt"), + //INST(&V::STRB_imm_3, "STRB (immediate)", "0011100100iiiiiiiiiiiinnnnnttttt"), + //INST(&V::LDRB_imm_1, "LDRB (immediate)", "00111000010iiiiiiiii01nnnnnttttt"), + //INST(&V::LDRB_imm_2, "LDRB (immediate)", "00111000010iiiiiiiii11nnnnnttttt"), + //INST(&V::LDRB_imm_3, "LDRB (immediate)", "0011100101iiiiiiiiiiiinnnnnttttt"), + //INST(&V::LDRSB_imm_1, "LDRSB (immediate)", "001110001-0iiiiiiiii01nnnnnttttt"), + //INST(&V::LDRSB_imm_2, "LDRSB (immediate)", "001110001-0iiiiiiiii11nnnnnttttt"), + //INST(&V::LDRSB_imm_3, "LDRSB (immediate)", "001110011-iiiiiiiiiiiinnnnnttttt"), + //INST(&V::STR_imm_fpsimd_1, "STR (immediate, SIMD&FP)", "zz111100-00iiiiiiiii01nnnnnttttt"), + //INST(&V::STR_imm_fpsimd_2, "STR (immediate, SIMD&FP)", "zz111100-00iiiiiiiii11nnnnnttttt"), + //INST(&V::STR_imm_fpsimd_3, "STR (immediate, SIMD&FP)", "zz111101-0iiiiiiiiiiiinnnnnttttt"), + //INST(&V::LDR_imm_fpsimd_1, "LDR (immediate, SIMD&FP)", "zz111100-10iiiiiiiii01nnnnnttttt"), + //INST(&V::LDR_imm_fpsimd_2, "LDR (immediate, SIMD&FP)", "zz111100-10iiiiiiiii11nnnnnttttt"), + //INST(&V::LDR_imm_fpsimd_3, "LDR (immediate, SIMD&FP)", "zz111101-1iiiiiiiiiiiinnnnnttttt"), + //INST(&V::STRH_imm_1, "STRH (immediate)", "01111000000iiiiiiiii01nnnnnttttt"), + //INST(&V::STRH_imm_2, "STRH (immediate)", "01111000000iiiiiiiii11nnnnnttttt"), + //INST(&V::STRH_imm_3, "STRH (immediate)", "0111100100iiiiiiiiiiiinnnnnttttt"), + //INST(&V::LDRH_imm_1, "LDRH (immediate)", "01111000010iiiiiiiii01nnnnnttttt"), + //INST(&V::LDRH_imm_2, "LDRH (immediate)", "01111000010iiiiiiiii11nnnnnttttt"), + //INST(&V::LDRH_imm_3, "LDRH (immediate)", "0111100101iiiiiiiiiiiinnnnnttttt"), + //INST(&V::LDRSH_imm_1, "LDRSH (immediate)", "011110001-0iiiiiiiii01nnnnnttttt"), + //INST(&V::LDRSH_imm_2, "LDRSH (immediate)", "011110001-0iiiiiiiii11nnnnnttttt"), + //INST(&V::LDRSH_imm_3, "LDRSH (immediate)", "011110011-iiiiiiiiiiiinnnnnttttt"), + //INST(&V::STR_imm_gen_1, "STR (immediate)", "1-111000000iiiiiiiii01nnnnnttttt"), + //INST(&V::STR_imm_gen_2, "STR (immediate)", "1-111000000iiiiiiiii11nnnnnttttt"), + //INST(&V::STR_imm_gen_3, "STR (immediate)", "1-11100100iiiiiiiiiiiinnnnnttttt"), + //INST(&V::LDR_imm_gen_1, "LDR (immediate)", "1-111000010iiiiiiiii01nnnnnttttt"), + //INST(&V::LDR_imm_gen_2, "LDR (immediate)", "1-111000010iiiiiiiii11nnnnnttttt"), + //INST(&V::LDR_imm_gen_3, "LDR (immediate)", "1-11100101iiiiiiiiiiiinnnnnttttt"), + //INST(&V::LDRSW_imm_1, "LDRSW (immediate)", "10111000100iiiiiiiii01nnnnnttttt"), + //INST(&V::LDRSW_imm_2, "LDRSW (immediate)", "10111000100iiiiiiiii11nnnnnttttt"), + //INST(&V::LDRSW_imm_3, "LDRSW (immediate)", "1011100110iiiiiiiiiiiinnnnnttttt"), + + // Loads and stores - Load/Store register (unprivileged) + //INST(&V::STTRB, "STTRB", "00111000000iiiiiiiii10nnnnnttttt"), + //INST(&V::LDTRB, "LDTRB", "00111000010iiiiiiiii10nnnnnttttt"), + //INST(&V::LDTRSB, "LDTRSB", "001110001-0iiiiiiiii10nnnnnttttt"), + //INST(&V::STTRH, "STTRH", "01111000000iiiiiiiii10nnnnnttttt"), + //INST(&V::LDTRH, "LDTRH", "01111000010iiiiiiiii10nnnnnttttt"), + //INST(&V::LDTRSH, "LDTRSH", "011110001-0iiiiiiiii10nnnnnttttt"), + //INST(&V::STTR, "STTR", "1-111000000iiiiiiiii10nnnnnttttt"), + //INST(&V::LDTR, "LDTR", "1-111000010iiiiiiiii10nnnnnttttt"), + //INST(&V::LDTRSW, "LDTRSW", "10111000100iiiiiiiii10nnnnnttttt"), + + // Loads and stores - Atomic memory options + //INST(&V::LDADDB, "LDADDB, LDADDAB, LDADDALB, LDADDLB", "00111000AR1sssss000000nnnnnttttt"), + //INST(&V::LDCLRB, "LDCLRB, LDCLRAB, LDCLRALB, LDCLRLB", "00111000AR1sssss000100nnnnnttttt"), + //INST(&V::LDEORB, "LDEORB, LDEORAB, LDEORALB, LDEORLB", "00111000AR1sssss001000nnnnnttttt"), + //INST(&V::LDSETB, "LDSETB, LDSETAB, LDSETALB, LDSETLB", "00111000AR1sssss001100nnnnnttttt"), + //INST(&V::LDSMAXB, "LDSMAXB, LDSMAXAB, LDSMAXALB, LDSMAXLB", "00111000AR1sssss010000nnnnnttttt"), + //INST(&V::LDSMINB, "LDSMINB, LDSMINAB, LDSMINALB, LDSMINLB", "00111000AR1sssss010100nnnnnttttt"), + //INST(&V::LDUMAXB, "LDUMAXB, LDUMAXAB, LDUMAXALB, LDUMAXLB", "00111000AR1sssss011000nnnnnttttt"), + //INST(&V::LDUMINB, "LDUMINB, LDUMINAB, LDUMINALB, LDUMINLB", "00111000AR1sssss011100nnnnnttttt"), + //INST(&V::SWPB, "SWPB, SWPAB, SWPALB, SWPLB", "00111000AR1sssss100000nnnnnttttt"), + //INST(&V::LDAPRB, "LDAPRB", "0011100010111111110000nnnnnttttt"), + //INST(&V::LDADDH, "LDADDH, LDADDAH, LDADDALH, LDADDLH", "01111000AR1sssss000000nnnnnttttt"), + //INST(&V::LDCLRH, "LDCLRH, LDCLRAH, LDCLRALH, LDCLRLH", "01111000AR1sssss000100nnnnnttttt"), + //INST(&V::LDEORH, "LDEORH, LDEORAH, LDEORALH, LDEORLH", "01111000AR1sssss001000nnnnnttttt"), + //INST(&V::LDSETH, "LDSETH, LDSETAH, LDSETALH, LDSETLH", "01111000AR1sssss001100nnnnnttttt"), + //INST(&V::LDSMAXH, "LDSMAXH, LDSMAXAH, LDSMAXALH, LDSMAXLH", "01111000AR1sssss010000nnnnnttttt"), + //INST(&V::LDSMINH, "LDSMINH, LDSMINAH, LDSMINALH, LDSMINLH", "01111000AR1sssss010100nnnnnttttt"), + //INST(&V::LDUMAXH, "LDUMAXH, LDUMAXAH, LDUMAXALH, LDUMAXLH", "01111000AR1sssss011000nnnnnttttt"), + //INST(&V::LDUMINH, "LDUMINH, LDUMINAH, LDUMINALH, LDUMINLH", "01111000AR1sssss011100nnnnnttttt"), + //INST(&V::SWPH, "SWPH, SWPAH, SWPALH, SWPLH", "01111000AR1sssss100000nnnnnttttt"), + //INST(&V::LDAPRH, "LDAPRH", "0111100010111111110000nnnnnttttt"), + //INST(&V::LDADD, "LDADD, LDADDA, LDADDAL, LDADDL", "1-111000AR1sssss000000nnnnnttttt"), + //INST(&V::LDCLR, "LDCLR, LDCLRA, LDCLRAL, LDCLRL", "1-111000AR1sssss000100nnnnnttttt"), + //INST(&V::LDEOR, "LDEOR, LDEORA, LDEORAL, LDEORL", "1-111000AR1sssss001000nnnnnttttt"), + //INST(&V::LDSET, "LDSET, LDSETA, LDSETAL, LDSETL", "1-111000AR1sssss001100nnnnnttttt"), + //INST(&V::LDSMAX, "LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL", "1-111000AR1sssss010000nnnnnttttt"), + //INST(&V::LDSMIN, "LDSMIN, LDSMINA, LDSMINAL, LDSMINL", "1-111000AR1sssss010100nnnnnttttt"), + //INST(&V::LDUMAX, "LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL", "1-111000AR1sssss011000nnnnnttttt"), + //INST(&V::LDUMIN, "LDUMIN, LDUMINA, LDUMINAL, LDUMINL", "1-111000AR1sssss011100nnnnnttttt"), + //INST(&V::SWP, "SWP, SWPA, SWPAL, SWPL", "1-111000AR1sssss100000nnnnnttttt"), + //INST(&V::LDAPR, "LDAPR", "1-11100010111111110000nnnnnttttt"), + + // Loads and stores - Load/Store register (register offset) + //INST(&V::STRB_reg, "STRB (register)", "00111000001mmmmmxxxS10nnnnnttttt"), + //INST(&V::LDRB_reg, "LDRB (register)", "00111000011mmmmmxxxS10nnnnnttttt"), + //INST(&V::LDRSB_reg, "LDRSB (register)", "001110001-1mmmmmxxxS10nnnnnttttt"), + //INST(&V::STR_reg_fpsimd, "STR (register, SIMD&FP)", "zz111100-01mmmmmxxxS10nnnnnttttt"), + //INST(&V::LDR_reg_fpsimd, "LDR (register, SIMD&FP)", "zz111100-11mmmmmxxxS10nnnnnttttt"), + //INST(&V::STRH_reg, "STRH (register)", "01111000001mmmmmxxxS10nnnnnttttt"), + //INST(&V::LDRH_reg, "LDRH (register)", "01111000011mmmmmxxxS10nnnnnttttt"), + //INST(&V::LDRSH_reg, "LDRSH (register)", "011110001-1mmmmmxxxS10nnnnnttttt"), + //INST(&V::STR_reg_gen, "STR (register)", "1-111000001mmmmmxxxS10nnnnnttttt"), + //INST(&V::LDR_reg_gen, "LDR (register)", "1-111000011mmmmmxxxS10nnnnnttttt"), + //INST(&V::LDRSW_reg, "LDRSW (register)", "10111000101mmmmmxxxS10nnnnnttttt"), + //INST(&V::PRFM_reg, "PRFM (register)", "11111000101mmmmmxxxS10nnnnnttttt"), + + // Loads and stores - Load/Store register (pointer authentication) + //INST(&V::LDRA, "LDRAA, LDRAB", "11111000MS1iiiiiiiiiW1nnnnnttttt"), + + // Data Processing - Register - 2 source + //INST(&V::UDIV, "UDIV", "z0011010110mmmmm000010nnnnnddddd"), + //INST(&V::SDIV, "SDIV", "z0011010110mmmmm000011nnnnnddddd"), + //INST(&V::LSLV, "LSLV", "z0011010110mmmmm001000nnnnnddddd"), + //INST(&V::LSRV, "LSRV", "z0011010110mmmmm001001nnnnnddddd"), + //INST(&V::ASRV, "ASRV", "z0011010110mmmmm001010nnnnnddddd"), + //INST(&V::RORV, "RORV", "z0011010110mmmmm001011nnnnnddddd"), + //INST(&V::CRC32, "CRC32B, CRC32H, CRC32W, CRC32X", "z0011010110mmmmm0100zznnnnnddddd"), + //INST(&V::CRC32C, "CRC32CB, CRC32CH, CRC32CW, CRC32CX", "z0011010110mmmmm0101zznnnnnddddd"), + //INST(&V::PACGA, "PACGA", "10011010110mmmmm001100nnnnnddddd"), + + // Data Processing - Register - 1 source + //INST(&V::RBIT_int, "RBIT", "z101101011000000000000nnnnnddddd"), + //INST(&V::REV16_int, "REV16", "z101101011000000000001nnnnnddddd"), + //INST(&V::REV, "REV", "z10110101100000000001-nnnnnddddd"), + //INST(&V::CLZ_int, "CLZ", "z101101011000000000100nnnnnddddd"), + //INST(&V::CLS_int, "CLS", "z101101011000000000101nnnnnddddd"), + //INST(&V::REV32_int, "REV32", "1101101011000000000010nnnnnddddd"), + //INST(&V::PACDA, "PACDA, PACDZA", "110110101100000100Z010nnnnnddddd"), + //INST(&V::PACDB, "PACDB, PACDZB", "110110101100000100Z011nnnnnddddd"), + //INST(&V::AUTDA, "AUTDA, AUTDZA", "110110101100000100Z110nnnnnddddd"), + //INST(&V::AUTDB, "AUTDB, AUTDZB", "110110101100000100Z111nnnnnddddd"), + + // Data Processing - Register - Logical (shifted register) + //INST(&V::AND_shift, "AND (shifted register)", "z0001010ss0mmmmmiiiiiinnnnnddddd"), + //INST(&V::BIC_shift, "BIC (shifted register)", "z0001010ss1mmmmmiiiiiinnnnnddddd"), + //INST(&V::ORR_shift, "ORR (shifted register)", "z0101010ss0mmmmmiiiiiinnnnnddddd"), + //INST(&V::ORN_shift, "ORN (shifted register)", "z0101010ss1mmmmmiiiiiinnnnnddddd"), + //INST(&V::EOR_shift, "EOR (shifted register)", "z1001010ss0mmmmmiiiiiinnnnnddddd"), + //INST(&V::EON, "EON (shifted register)", "z1001010ss1mmmmmiiiiiinnnnnddddd"), + //INST(&V::ANDS_shift, "ANDS (shifted register)", "z1101010ss0mmmmmiiiiiinnnnnddddd"), + //INST(&V::BICS, "BICS (shifted register)", "z1101010ss1mmmmmiiiiiinnnnnddddd"), + + // Data Processing - Register - Add/Sub (shifted register) + //INST(&V::ADD_shift, "ADD (shifted register)", "z0001011ss0mmmmmiiiiiinnnnnddddd"), + //INST(&V::ADDS_shift, "ADDS (shifted register)", "z0101011ss0mmmmmiiiiiinnnnnddddd"), + //INST(&V::SUB_shift, "SUB (shifted register)", "z1001011ss0mmmmmiiiiiinnnnnddddd"), + //INST(&V::SUBS_shift, "SUBS (shifted register)", "z1101011ss0mmmmmiiiiiinnnnnddddd"), + + // Data Processing - Register - Add/Sub (shifted register) + //INST(&V::ADD_ext, "ADD (extended register)", "z0001011001mmmmmxxxiiinnnnnddddd"), + //INST(&V::ADDS_ext, "ADDS (extended register)", "z0101011001mmmmmxxxiiinnnnnddddd"), + //INST(&V::SUB_ext, "SUB (extended register)", "z1001011001mmmmmxxxiiinnnnnddddd"), + //INST(&V::SUBS_ext, "SUBS (extended register)", "z1101011001mmmmmxxxiiinnnnnddddd"), + + // Data Processing - Register - Add/Sub (with carry) + //INST(&V::ADC, "ADC", "z0011010000mmmmm000000nnnnnddddd"), + //INST(&V::ADCS, "ADCS", "z0111010000mmmmm000000nnnnnddddd"), + //INST(&V::SBC, "SBC", "z1011010000mmmmm000000nnnnnddddd"), + //INST(&V::SBCS, "SBCS", "z1111010000mmmmm000000nnnnnddddd"), + + // Data Processing - Register - Conditional compare + //INST(&V::CCMN_reg, "CCMN (register)", "z0111010010mmmmmcccc00nnnnn0ffff"), + //INST(&V::CCMP_reg, "CCMP (register)", "z1111010010mmmmmcccc00nnnnn0ffff"), + //INST(&V::CCMN_imm, "CCMN (immediate)", "z0111010010iiiiicccc10nnnnn0ffff"), + //INST(&V::CCMP_imm, "CCMP (immediate)", "z1111010010iiiiicccc10nnnnn0ffff"), + + // Data Processing - Register - Conditional select + //INST(&V::CSEL, "CSEL", "z0011010100mmmmmcccc00nnnnnddddd"), + //INST(&V::CSINC, "CSINC", "z0011010100mmmmmcccc01nnnnnddddd"), + //INST(&V::CSINV, "CSINV", "z1011010100mmmmmcccc00nnnnnddddd"), + //INST(&V::CSNEG, "CSNEG", "z1011010100mmmmmcccc01nnnnnddddd"), + + // Data Processing - Register - 3 source + //INST(&V::MADD, "MADD", "z0011011000mmmmm0aaaaannnnnddddd"), + //INST(&V::MSUB, "MSUB", "z0011011000mmmmm1aaaaannnnnddddd"), + //INST(&V::SMADDL, "SMADDL", "10011011001mmmmm0aaaaannnnnddddd"), + //INST(&V::SMSUBL, "SMSUBL", "10011011001mmmmm1aaaaannnnnddddd"), + //INST(&V::SMULH, "SMULH", "10011011010mmmmm011111nnnnnddddd"), + //INST(&V::UMADDL, "UMADDL", "10011011101mmmmm0aaaaannnnnddddd"), + //INST(&V::UMSUBL, "UMSUBL", "10011011101mmmmm1aaaaannnnnddddd"), + //INST(&V::UMULH, "UMULH", "10011011110mmmmm011111nnnnnddddd"), + + // Data Processing - FP and SIMD - AES + //INST(&V::AESE, "AESE", "0100111000101000010010nnnnnddddd"), + //INST(&V::AESD, "AESD", "0100111000101000010110nnnnnddddd"), + //INST(&V::AESMC, "AESMC", "0100111000101000011010nnnnnddddd"), + //INST(&V::AESIMC, "AESIMC", "0100111000101000011110nnnnnddddd"), + + // Data Processing - FP and SIMD - SHA + //INST(&V::SHA1C, "SHA1C", "01011110000mmmmm000000nnnnnddddd"), + //INST(&V::SHA1P, "SHA1P", "01011110000mmmmm000100nnnnnddddd"), + //INST(&V::SHA1M, "SHA1M", "01011110000mmmmm001000nnnnnddddd"), + //INST(&V::SHA1SU0, "SHA1SU0", "01011110000mmmmm001100nnnnnddddd"), + //INST(&V::SHA256H, "SHA256H", "01011110000mmmmm010000nnnnnddddd"), + //INST(&V::SHA256H2, "SHA256H2", "01011110000mmmmm010100nnnnnddddd"), + //INST(&V::SHA256SU1, "SHA256SU1", "01011110000mmmmm011000nnnnnddddd"), + //INST(&V::SHA1H, "SHA1H", "0101111000101000000010nnnnnddddd"), + //INST(&V::SHA1SU1, "SHA1SU1", "0101111000101000000110nnnnnddddd"), + //INST(&V::SHA256SU0, "SHA256SU0", "0101111000101000001010nnnnnddddd"), + + // Data Processing - FP and SIMD - Scalar copy + //INST(&V::DUP_elt_1, "DUP (element)", "01011110000iiiii000001nnnnnddddd"), + //INST(&V::DUP_elt_2, "DUP (element)", "0Q001110000iiiii000001nnnnnddddd"), + + // Data Processing - FP and SIMD - Scalar three + //INST(&V::FMULX_vec_1, "FMULX", "01011110010mmmmm000111nnnnnddddd"), + //INST(&V::FMULX_vec_2, "FMULX", "010111100z1mmmmm110111nnnnnddddd"), + //INST(&V::FMULX_vec_3, "FMULX", "0Q001110010mmmmm000111nnnnnddddd"), + //INST(&V::FMULX_vec_4, "FMULX", "0Q0011100z1mmmmm110111nnnnnddddd"), + //INST(&V::FCMEQ_reg_1, "FCMEQ (register)", "01011110010mmmmm001001nnnnnddddd"), + //INST(&V::FCMEQ_reg_2, "FCMEQ (register)", "010111100z1mmmmm111001nnnnnddddd"), + //INST(&V::FCMEQ_reg_3, "FCMEQ (register)", "0Q001110010mmmmm001001nnnnnddddd"), + //INST(&V::FCMEQ_reg_4, "FCMEQ (register)", "0Q0011100z1mmmmm111001nnnnnddddd"), + //INST(&V::FRECPS_1, "FRECPS", "01011110010mmmmm001111nnnnnddddd"), + //INST(&V::FRECPS_2, "FRECPS", "010111100z1mmmmm111111nnnnnddddd"), + //INST(&V::FRECPS_3, "FRECPS", "0Q001110010mmmmm001111nnnnnddddd"), + //INST(&V::FRECPS_4, "FRECPS", "0Q0011100z1mmmmm111111nnnnnddddd"), + //INST(&V::FRSQRTS_1, "FRSQRTS", "01011110110mmmmm001111nnnnnddddd"), + //INST(&V::FRSQRTS_2, "FRSQRTS", "010111101z1mmmmm111111nnnnnddddd"), + //INST(&V::FRSQRTS_3, "FRSQRTS", "0Q001110110mmmmm001111nnnnnddddd"), + //INST(&V::FRSQRTS_4, "FRSQRTS", "0Q0011101z1mmmmm111111nnnnnddddd"), + //INST(&V::FCMGE_reg_1, "FCMGE (register)", "01111110010mmmmm001001nnnnnddddd"), + //INST(&V::FCMGE_reg_2, "FCMGE (register)", "011111100z1mmmmm111001nnnnnddddd"), + //INST(&V::FCMGE_reg_3, "FCMGE (register)", "0Q101110010mmmmm001001nnnnnddddd"), + //INST(&V::FCMGE_reg_4, "FCMGE (register)", "0Q1011100z1mmmmm111001nnnnnddddd"), + //INST(&V::FACGE_1, "FACGE", "01111110010mmmmm001011nnnnnddddd"), + //INST(&V::FACGE_2, "FACGE", "011111100z1mmmmm111011nnnnnddddd"), + //INST(&V::FACGE_3, "FACGE", "0Q101110010mmmmm001011nnnnnddddd"), + //INST(&V::FACGE_4, "FACGE", "0Q1011100z1mmmmm111011nnnnnddddd"), + //INST(&V::FABD_1, "FABD", "01111110110mmmmm000101nnnnnddddd"), + //INST(&V::FABD_2, "FABD", "011111101z1mmmmm110101nnnnnddddd"), + //INST(&V::FABD_3, "FABD", "0Q101110110mmmmm000101nnnnnddddd"), + //INST(&V::FABD_4, "FABD", "0Q1011101z1mmmmm110101nnnnnddddd"), + //INST(&V::FCMGT_reg_1, "FCMGT (register)", "01111110110mmmmm001001nnnnnddddd"), + //INST(&V::FCMGT_reg_2, "FCMGT (register)", "011111101z1mmmmm111001nnnnnddddd"), + //INST(&V::FCMGT_reg_3, "FCMGT (register)", "0Q101110110mmmmm001001nnnnnddddd"), + //INST(&V::FCMGT_reg_4, "FCMGT (register)", "0Q1011101z1mmmmm111001nnnnnddddd"), + //INST(&V::FACGT_1, "FACGT", "01111110110mmmmm001011nnnnnddddd"), + //INST(&V::FACGT_2, "FACGT", "011111101z1mmmmm111011nnnnnddddd"), + //INST(&V::FACGT_3, "FACGT", "0Q101110110mmmmm001011nnnnnddddd"), + //INST(&V::FACGT_4, "FACGT", "0Q1011101z1mmmmm111011nnnnnddddd"), + + // Data Processing - FP and SIMD - Two register misc + //INST(&V::FCVTNS_1, "FCVTNS (vector)", "0101111001111001101010nnnnnddddd"), + //INST(&V::FCVTNS_2, "FCVTNS (vector)", "010111100z100001101010nnnnnddddd"), + //INST(&V::FCVTNS_3, "FCVTNS (vector)", "0Q00111001111001101010nnnnnddddd"), + //INST(&V::FCVTNS_4, "FCVTNS (vector)", "0Q0011100z100001101010nnnnnddddd"), + //INST(&V::FCVTMS_1, "FCVTMS (vector)", "0101111001111001101110nnnnnddddd"), + //INST(&V::FCVTMS_2, "FCVTMS (vector)", "010111100z100001101110nnnnnddddd"), + //INST(&V::FCVTMS_3, "FCVTMS (vector)", "0Q00111001111001101110nnnnnddddd"), + //INST(&V::FCVTMS_4, "FCVTMS (vector)", "0Q0011100z100001101110nnnnnddddd"), + //INST(&V::FCVTAS_1, "FCVTAS (vector)", "0101111001111001110010nnnnnddddd"), + //INST(&V::FCVTAS_2, "FCVTAS (vector)", "010111100z100001110010nnnnnddddd"), + //INST(&V::FCVTAS_3, "FCVTAS (vector)", "0Q00111001111001110010nnnnnddddd"), + //INST(&V::FCVTAS_4, "FCVTAS (vector)", "0Q0011100z100001110010nnnnnddddd"), + //INST(&V::SCVTF_int_1, "SCVTF (vector, integer)", "0101111001111001110110nnnnnddddd"), + //INST(&V::SCVTF_int_2, "SCVTF (vector, integer)", "010111100z100001110110nnnnnddddd"), + //INST(&V::SCVTF_int_3, "SCVTF (vector, integer)", "0Q00111001111001110110nnnnnddddd"), + //INST(&V::SCVTF_int_4, "SCVTF (vector, integer)", "0Q0011100z100001110110nnnnnddddd"), + //INST(&V::FCMGT_zero_1, "FCMGT (zero)", "0101111011111000110010nnnnnddddd"), + //INST(&V::FCMGT_zero_2, "FCMGT (zero)", "010111101z100000110010nnnnnddddd"), + //INST(&V::FCMGT_zero_3, "FCMGT (zero)", "0Q00111011111000110010nnnnnddddd"), + //INST(&V::FCMGT_zero_4, "FCMGT (zero)", "0Q0011101z100000110010nnnnnddddd"), + //INST(&V::FCMEQ_zero_1, "FCMEQ (zero)", "0101111011111000110110nnnnnddddd"), + //INST(&V::FCMEQ_zero_2, "FCMEQ (zero)", "010111101z100000110110nnnnnddddd"), + //INST(&V::FCMEQ_zero_3, "FCMEQ (zero)", "0Q00111011111000110110nnnnnddddd"), + //INST(&V::FCMEQ_zero_4, "FCMEQ (zero)", "0Q0011101z100000110110nnnnnddddd"), + //INST(&V::FCMLT_1, "FCMLT (zero)", "0101111011111000111010nnnnnddddd"), + //INST(&V::FCMLT_2, "FCMLT (zero)", "010111101z100000111010nnnnnddddd"), + //INST(&V::FCMLT_3, "FCMLT (zero)", "0Q00111011111000111010nnnnnddddd"), + //INST(&V::FCMLT_4, "FCMLT (zero)", "0Q0011101z100000111010nnnnnddddd"), + //INST(&V::FCVTPS_1, "FCVTPS (vector)", "0101111011111001101010nnnnnddddd"), + //INST(&V::FCVTPS_2, "FCVTPS (vector)", "010111101z100001101010nnnnnddddd"), + //INST(&V::FCVTPS_3, "FCVTPS (vector)", "0Q00111011111001101010nnnnnddddd"), + //INST(&V::FCVTPS_4, "FCVTPS (vector)", "0Q0011101z100001101010nnnnnddddd"), + //INST(&V::FCVTZS_int_1, "FCVTZS (vector, integer)", "0101111011111001101110nnnnnddddd"), + //INST(&V::FCVTZS_int_2, "FCVTZS (vector, integer)", "010111101z100001101110nnnnnddddd"), + //INST(&V::FCVTZS_int_3, "FCVTZS (vector, integer)", "0Q00111011111001101110nnnnnddddd"), + //INST(&V::FCVTZS_int_4, "FCVTZS (vector, integer)", "0Q0011101z100001101110nnnnnddddd"), + //INST(&V::FRECPE_1, "FRECPE", "0101111011111001110110nnnnnddddd"), + //INST(&V::FRECPE_2, "FRECPE", "010111101z100001110110nnnnnddddd"), + //INST(&V::FRECPE_3, "FRECPE", "0Q00111011111001110110nnnnnddddd"), + //INST(&V::FRECPE_4, "FRECPE", "0Q0011101z100001110110nnnnnddddd"), + //INST(&V::FRECPX_1, "FRECPX", "0101111011111001111110nnnnnddddd"), + //INST(&V::FRECPX_2, "FRECPX", "010111101z100001111110nnnnnddddd"), + //INST(&V::FCVTNU_1, "FCVTNU (vector)", "0111111001111001101010nnnnnddddd"), + //INST(&V::FCVTNU_2, "FCVTNU (vector)", "011111100z100001101010nnnnnddddd"), + //INST(&V::FCVTNU_3, "FCVTNU (vector)", "0Q10111001111001101010nnnnnddddd"), + //INST(&V::FCVTNU_4, "FCVTNU (vector)", "0Q1011100z100001101010nnnnnddddd"), + //INST(&V::FCVTMU_1, "FCVTMU (vector)", "0111111001111001101110nnnnnddddd"), + //INST(&V::FCVTMU_2, "FCVTMU (vector)", "011111100z100001101110nnnnnddddd"), + //INST(&V::FCVTMU_3, "FCVTMU (vector)", "0Q10111001111001101110nnnnnddddd"), + //INST(&V::FCVTMU_4, "FCVTMU (vector)", "0Q1011100z100001101110nnnnnddddd"), + //INST(&V::FCVTAU_1, "FCVTAU (vector)", "0111111001111001110010nnnnnddddd"), + //INST(&V::FCVTAU_2, "FCVTAU (vector)", "011111100z100001110010nnnnnddddd"), + //INST(&V::FCVTAU_3, "FCVTAU (vector)", "0Q10111001111001110010nnnnnddddd"), + //INST(&V::FCVTAU_4, "FCVTAU (vector)", "0Q1011100z100001110010nnnnnddddd"), + //INST(&V::UCVTF_int_1, "UCVTF (vector, integer)", "0111111001111001110110nnnnnddddd"), + //INST(&V::UCVTF_int_2, "UCVTF (vector, integer)", "011111100z100001110110nnnnnddddd"), + //INST(&V::UCVTF_int_3, "UCVTF (vector, integer)", "0Q10111001111001110110nnnnnddddd"), + //INST(&V::UCVTF_int_4, "UCVTF (vector, integer)", "0Q1011100z100001110110nnnnnddddd"), + //INST(&V::FCMGE_zero_1, "FCMGE (zero)", "0111111011111000110010nnnnnddddd"), + //INST(&V::FCMGE_zero_2, "FCMGE (zero)", "011111101z100000110010nnnnnddddd"), + //INST(&V::FCMGE_zero_3, "FCMGE (zero)", "0Q10111011111000110010nnnnnddddd"), + //INST(&V::FCMGE_zero_4, "FCMGE (zero)", "0Q1011101z100000110010nnnnnddddd"), + //INST(&V::FCMLE_1, "FCMLE (zero)", "0111111011111000110110nnnnnddddd"), + //INST(&V::FCMLE_2, "FCMLE (zero)", "011111101z100000110110nnnnnddddd"), + //INST(&V::FCMLE_3, "FCMLE (zero)", "0Q10111011111000110110nnnnnddddd"), + //INST(&V::FCMLE_4, "FCMLE (zero)", "0Q1011101z100000110110nnnnnddddd"), + //INST(&V::FCVTPU_1, "FCVTPU (vector)", "0111111011111001101010nnnnnddddd"), + //INST(&V::FCVTPU_2, "FCVTPU (vector)", "011111101z100001101010nnnnnddddd"), + //INST(&V::FCVTPU_3, "FCVTPU (vector)", "0Q10111011111001101010nnnnnddddd"), + //INST(&V::FCVTPU_4, "FCVTPU (vector)", "0Q1011101z100001101010nnnnnddddd"), + //INST(&V::FCVTZU_int_1, "FCVTZU (vector, integer)", "0111111011111001101110nnnnnddddd"), + //INST(&V::FCVTZU_int_2, "FCVTZU (vector, integer)", "011111101z100001101110nnnnnddddd"), + //INST(&V::FCVTZU_int_3, "FCVTZU (vector, integer)", "0Q10111011111001101110nnnnnddddd"), + //INST(&V::FCVTZU_int_4, "FCVTZU (vector, integer)", "0Q1011101z100001101110nnnnnddddd"), + //INST(&V::FRSQRTE_1, "FRSQRTE", "0111111011111001110110nnnnnddddd"), + //INST(&V::FRSQRTE_2, "FRSQRTE", "011111101z100001110110nnnnnddddd"), + //INST(&V::FRSQRTE_3, "FRSQRTE", "0Q10111011111001110110nnnnnddddd"), + //INST(&V::FRSQRTE_4, "FRSQRTE", "0Q1011101z100001110110nnnnnddddd"), + + // Data Processing - FP and SIMD - Scalar three same extra + //INST(&V::SQRDMLAH_vec_1, "SQRDMLAH (vector)", "01111110zz0mmmmm100001nnnnnddddd"), + //INST(&V::SQRDMLAH_vec_2, "SQRDMLAH (vector)", "0Q101110zz0mmmmm100001nnnnnddddd"), + //INST(&V::SQRDMLSH_vec_1, "SQRDMLSH (vector)", "01111110zz0mmmmm100011nnnnnddddd"), + //INST(&V::SQRDMLSH_vec_2, "SQRDMLSH (vector)", "0Q101110zz0mmmmm100011nnnnnddddd"), + + // Data Processing - FP and SIMD - Scalar two-register misc + //INST(&V::SUQADD_1, "SUQADD", "01011110zz100000001110nnnnnddddd"), + //INST(&V::SUQADD_2, "SUQADD", "0Q001110zz100000001110nnnnnddddd"), + //INST(&V::SQABS_1, "SQABS", "01011110zz100000011110nnnnnddddd"), + //INST(&V::SQABS_2, "SQABS", "0Q001110zz100000011110nnnnnddddd"), + //INST(&V::CMGT_zero_1, "CMGT (zero)", "01011110zz100000100010nnnnnddddd"), + //INST(&V::CMGT_zero_2, "CMGT (zero)", "0Q001110zz100000100010nnnnnddddd"), + //INST(&V::CMEQ_zero_1, "CMEQ (zero)", "01011110zz100000100110nnnnnddddd"), + //INST(&V::CMEQ_zero_2, "CMEQ (zero)", "0Q001110zz100000100110nnnnnddddd"), + //INST(&V::CMLT_1, "CMLT (zero)", "01011110zz100000101010nnnnnddddd"), + //INST(&V::CMLT_2, "CMLT (zero)", "0Q001110zz100000101010nnnnnddddd"), + //INST(&V::ABS_1, "ABS", "01011110zz100000101110nnnnnddddd"), + //INST(&V::ABS_2, "ABS", "0Q001110zz100000101110nnnnnddddd"), + //INST(&V::SQXTN_1, "SQXTN, SQXTN2", "01011110zz100001010010nnnnnddddd"), + //INST(&V::SQXTN_2, "SQXTN, SQXTN2", "0Q001110zz100001010010nnnnnddddd"), + //INST(&V::USQADD_1, "USQADD", "01111110zz100000001110nnnnnddddd"), + //INST(&V::USQADD_2, "USQADD", "0Q101110zz100000001110nnnnnddddd"), + //INST(&V::SQNEG_1, "SQNEG", "01111110zz100000011110nnnnnddddd"), + //INST(&V::SQNEG_2, "SQNEG", "0Q101110zz100000011110nnnnnddddd"), + //INST(&V::CMGE_zero_1, "CMGE (zero)", "01111110zz100000100010nnnnnddddd"), + //INST(&V::CMGE_zero_2, "CMGE (zero)", "0Q101110zz100000100010nnnnnddddd"), + //INST(&V::CMLE_1, "CMLE (zero)", "01111110zz100000100110nnnnnddddd"), + //INST(&V::CMLE_2, "CMLE (zero)", "0Q101110zz100000100110nnnnnddddd"), + //INST(&V::NEG_1, "NEG (vector)", "01111110zz100000101110nnnnnddddd"), + //INST(&V::NEG_2, "NEG (vector)", "0Q101110zz100000101110nnnnnddddd"), + //INST(&V::SQXTUN_1, "SQXTUN, SQXTUN2", "01111110zz100001001010nnnnnddddd"), + //INST(&V::SQXTUN_2, "SQXTUN, SQXTUN2", "0Q101110zz100001001010nnnnnddddd"), + //INST(&V::UQXTN_1, "UQXTN, UQXTN2", "01111110zz100001010010nnnnnddddd"), + //INST(&V::UQXTN_2, "UQXTN, UQXTN2", "0Q101110zz100001010010nnnnnddddd"), + //INST(&V::FCVTXN_1, "FCVTXN, FCVTXN2", "011111100z100001011010nnnnnddddd"), + //INST(&V::FCVTXN_2, "FCVTXN, FCVTXN2", "0Q1011100z100001011010nnnnnddddd"), + + // Data Processing - FP and SIMD - SIMD Scalar pairwise + //INST(&V::ADDP_pair, "ADDP (scalar)", "01011110zz110001101110nnnnnddddd"), + //INST(&V::FMAXNMP_pair_1, "FMAXNMP (scalar)", "0101111000110000110010nnnnnddddd"), + //INST(&V::FMAXNMP_pair_2, "FMAXNMP (scalar)", "011111100z110000110010nnnnnddddd"), + //INST(&V::FADDP_pair_1, "FADDP (scalar)", "0101111000110000110110nnnnnddddd"), + //INST(&V::FADDP_pair_2, "FADDP (scalar)", "011111100z110000110110nnnnnddddd"), + //INST(&V::FMAXP_pair_1, "FMAXP (scalar)", "0101111000110000111110nnnnnddddd"), + //INST(&V::FMAXP_pair_2, "FMAXP (scalar)", "011111100z110000111110nnnnnddddd"), + //INST(&V::FMINNMP_pair_1, "FMINNMP (scalar)", "0101111010110000110010nnnnnddddd"), + //INST(&V::FMINNMP_pair_2, "FMINNMP (scalar)", "011111101z110000110010nnnnnddddd"), + //INST(&V::FMINP_pair_1, "FMINP (scalar)", "0101111010110000111110nnnnnddddd"), + //INST(&V::FMINP_pair_2, "FMINP (scalar)", "011111101z110000111110nnnnnddddd"), + + // Data Processing - FP and SIMD - SIMD Scalar three different + //INST(&V::SQDMLAL_vec_1, "SQDMLAL, SQDMLAL2 (vector)", "01011110zz1mmmmm100100nnnnnddddd"), + //INST(&V::SQDMLAL_vec_2, "SQDMLAL, SQDMLAL2 (vector)", "0Q001110zz1mmmmm100100nnnnnddddd"), + //INST(&V::SQDMLSL_vec_1, "SQDMLSL, SQDMLSL2 (vector)", "01011110zz1mmmmm101100nnnnnddddd"), + //INST(&V::SQDMLSL_vec_2, "SQDMLSL, SQDMLSL2 (vector)", "0Q001110zz1mmmmm101100nnnnnddddd"), + //INST(&V::SQDMULL_vec_1, "SQDMULL, SQDMULL2 (vector)", "01011110zz1mmmmm110100nnnnnddddd"), + //INST(&V::SQDMULL_vec_2, "SQDMULL, SQDMULL2 (vector)", "0Q001110zz1mmmmm110100nnnnnddddd"), + + // Data Processing - FP and SIMD - SIMD Scalar three same + //INST(&V::SQADD_1, "SQADD", "01011110zz1mmmmm000011nnnnnddddd"), + //INST(&V::SQADD_2, "SQADD", "0Q001110zz1mmmmm000011nnnnnddddd"), + //INST(&V::SQSUB_1, "SQSUB", "01011110zz1mmmmm001011nnnnnddddd"), + //INST(&V::SQSUB_2, "SQSUB", "0Q001110zz1mmmmm001011nnnnnddddd"), + //INST(&V::CMGT_reg_1, "CMGT (register)", "01011110zz1mmmmm001101nnnnnddddd"), + //INST(&V::CMGT_reg_2, "CMGT (register)", "0Q001110zz1mmmmm001101nnnnnddddd"), + //INST(&V::CMGE_reg_1, "CMGE (register)", "01011110zz1mmmmm001111nnnnnddddd"), + //INST(&V::CMGE_reg_2, "CMGE (register)", "0Q001110zz1mmmmm001111nnnnnddddd"), + //INST(&V::SSHL_1, "SSHL", "01011110zz1mmmmm010001nnnnnddddd"), + //INST(&V::SSHL_2, "SSHL", "0Q001110zz1mmmmm010001nnnnnddddd"), + //INST(&V::SQSHL_reg_1, "SQSHL (register)", "01011110zz1mmmmm010011nnnnnddddd"), + //INST(&V::SQSHL_reg_2, "SQSHL (register)", "0Q001110zz1mmmmm010011nnnnnddddd"), + //INST(&V::SRSHL_1, "SRSHL", "01011110zz1mmmmm010101nnnnnddddd"), + //INST(&V::SRSHL_2, "SRSHL", "0Q001110zz1mmmmm010101nnnnnddddd"), + //INST(&V::SQRSHL_1, "SQRSHL", "01011110zz1mmmmm010111nnnnnddddd"), + //INST(&V::SQRSHL_2, "SQRSHL", "0Q001110zz1mmmmm010111nnnnnddddd"), + //INST(&V::ADD_1, "ADD (vector)", "01011110zz1mmmmm100001nnnnnddddd"), + //INST(&V::ADD_2, "ADD (vector)", "0Q001110zz1mmmmm100001nnnnnddddd"), + //INST(&V::CMTST_1, "CMTST", "01011110zz1mmmmm100011nnnnnddddd"), + //INST(&V::CMTST_2, "CMTST", "0Q001110zz1mmmmm100011nnnnnddddd"), + //INST(&V::SQDMULH_vec_1, "SQDMULH (vector)", "01011110zz1mmmmm101101nnnnnddddd"), + //INST(&V::SQDMULH_vec_2, "SQDMULH (vector)", "0Q001110zz1mmmmm101101nnnnnddddd"), + //INST(&V::UQADD_1, "UQADD", "01111110zz1mmmmm000011nnnnnddddd"), + //INST(&V::UQADD_2, "UQADD", "0Q101110zz1mmmmm000011nnnnnddddd"), + //INST(&V::UQSUB_1, "UQSUB", "01111110zz1mmmmm001011nnnnnddddd"), + //INST(&V::UQSUB_2, "UQSUB", "0Q101110zz1mmmmm001011nnnnnddddd"), + //INST(&V::CMHI_1, "CMHI (register)", "01111110zz1mmmmm001101nnnnnddddd"), + //INST(&V::CMHI_2, "CMHI (register)", "0Q101110zz1mmmmm001101nnnnnddddd"), + //INST(&V::CMHS_1, "CMHS (register)", "01111110zz1mmmmm001111nnnnnddddd"), + //INST(&V::CMHS_2, "CMHS (register)", "0Q101110zz1mmmmm001111nnnnnddddd"), + //INST(&V::USHL_1, "USHL", "01111110zz1mmmmm010001nnnnnddddd"), + //INST(&V::USHL_2, "USHL", "0Q101110zz1mmmmm010001nnnnnddddd"), + //INST(&V::UQSHL_reg_1, "UQSHL (register)", "01111110zz1mmmmm010011nnnnnddddd"), + //INST(&V::UQSHL_reg_2, "UQSHL (register)", "0Q101110zz1mmmmm010011nnnnnddddd"), + //INST(&V::URSHL_1, "URSHL", "01111110zz1mmmmm010101nnnnnddddd"), + //INST(&V::URSHL_2, "URSHL", "0Q101110zz1mmmmm010101nnnnnddddd"), + //INST(&V::UQRSHL_1, "UQRSHL", "01111110zz1mmmmm010111nnnnnddddd"), + //INST(&V::UQRSHL_2, "UQRSHL", "0Q101110zz1mmmmm010111nnnnnddddd"), + //INST(&V::SUB_1, "SUB (vector)", "01111110zz1mmmmm100001nnnnnddddd"), + //INST(&V::SUB_2, "SUB (vector)", "0Q101110zz1mmmmm100001nnnnnddddd"), + //INST(&V::CMEQ_reg_1, "CMEQ (register)", "01111110zz1mmmmm100011nnnnnddddd"), + //INST(&V::CMEQ_reg_2, "CMEQ (register)", "0Q101110zz1mmmmm100011nnnnnddddd"), + //INST(&V::SQRDMULH_vec_1, "SQRDMULH (vector)", "01111110zz1mmmmm101101nnnnnddddd"), + //INST(&V::SQRDMULH_vec_2, "SQRDMULH (vector)", "0Q101110zz1mmmmm101101nnnnnddddd"), + + // Data Processing - FP and SIMD - SIMD Scalar shift by immediate + //INST(&V::SSHR_1, "SSHR", "010111110IIIIiii000001nnnnnddddd"), + //INST(&V::SSHR_2, "SSHR", "0Q0011110IIIIiii000001nnnnnddddd"), + //INST(&V::SSRA_1, "SSRA", "010111110IIIIiii000101nnnnnddddd"), + //INST(&V::SSRA_2, "SSRA", "0Q0011110IIIIiii000101nnnnnddddd"), + //INST(&V::SRSHR_1, "SRSHR", "010111110IIIIiii001001nnnnnddddd"), + //INST(&V::SRSHR_2, "SRSHR", "0Q0011110IIIIiii001001nnnnnddddd"), + //INST(&V::SRSRA_1, "SRSRA", "010111110IIIIiii001101nnnnnddddd"), + //INST(&V::SRSRA_2, "SRSRA", "0Q0011110IIIIiii001101nnnnnddddd"), + //INST(&V::SHL_1, "SHL", "010111110IIIIiii010101nnnnnddddd"), + //INST(&V::SHL_2, "SHL", "0Q0011110IIIIiii010101nnnnnddddd"), + //INST(&V::SQSHL_imm_1, "SQSHL (immediate)", "010111110IIIIiii011101nnnnnddddd"), + //INST(&V::SQSHL_imm_2, "SQSHL (immediate)", "0Q0011110IIIIiii011101nnnnnddddd"), + //INST(&V::SQSHRN_1, "SQSHRN, SQSHRN2", "010111110IIIIiii100101nnnnnddddd"), + //INST(&V::SQSHRN_2, "SQSHRN, SQSHRN2", "0Q0011110IIIIiii100101nnnnnddddd"), + //INST(&V::SQRSHRN_1, "SQRSHRN, SQRSHRN2", "010111110IIIIiii100111nnnnnddddd"), + //INST(&V::SQRSHRN_2, "SQRSHRN, SQRSHRN2", "0Q0011110IIIIiii100111nnnnnddddd"), + //INST(&V::SCVTF_fix_1, "SCVTF (vector, fixed-point)", "010111110IIIIiii111001nnnnnddddd"), + //INST(&V::SCVTF_fix_2, "SCVTF (vector, fixed-point)", "0Q0011110IIIIiii111001nnnnnddddd"), + //INST(&V::FCVTZS_fix_1, "FCVTZS (vector, fixed-point)", "010111110IIIIiii111111nnnnnddddd"), + //INST(&V::FCVTZS_fix_2, "FCVTZS (vector, fixed-point)", "0Q0011110IIIIiii111111nnnnnddddd"), + //INST(&V::USHR_1, "USHR", "011111110IIIIiii000001nnnnnddddd"), + //INST(&V::USHR_2, "USHR", "0Q1011110IIIIiii000001nnnnnddddd"), + //INST(&V::USRA_1, "USRA", "011111110IIIIiii000101nnnnnddddd"), + //INST(&V::USRA_2, "USRA", "0Q1011110IIIIiii000101nnnnnddddd"), + //INST(&V::URSHR_1, "URSHR", "011111110IIIIiii001001nnnnnddddd"), + //INST(&V::URSHR_2, "URSHR", "0Q1011110IIIIiii001001nnnnnddddd"), + //INST(&V::URSRA_1, "URSRA", "011111110IIIIiii001101nnnnnddddd"), + //INST(&V::URSRA_2, "URSRA", "0Q1011110IIIIiii001101nnnnnddddd"), + //INST(&V::SRI_1, "SRI", "011111110IIIIiii010001nnnnnddddd"), + //INST(&V::SRI_2, "SRI", "0Q1011110IIIIiii010001nnnnnddddd"), + //INST(&V::SLI_1, "SLI", "011111110IIIIiii010101nnnnnddddd"), + //INST(&V::SLI_2, "SLI", "0Q1011110IIIIiii010101nnnnnddddd"), + //INST(&V::SQSHLU_1, "SQSHLU", "011111110IIIIiii011001nnnnnddddd"), + //INST(&V::SQSHLU_2, "SQSHLU", "0Q1011110IIIIiii011001nnnnnddddd"), + //INST(&V::UQSHL_imm_1, "UQSHL (immediate)", "011111110IIIIiii011101nnnnnddddd"), + //INST(&V::UQSHL_imm_2, "UQSHL (immediate)", "0Q1011110IIIIiii011101nnnnnddddd"), + //INST(&V::SQSHRUN_1, "SQSHRUN, SQSHRUN2", "011111110IIIIiii100001nnnnnddddd"), + //INST(&V::SQSHRUN_2, "SQSHRUN, SQSHRUN2", "0Q1011110IIIIiii100001nnnnnddddd"), + //INST(&V::SQRSHRUN_1, "SQRSHRUN, SQRSHRUN2", "011111110IIIIiii100011nnnnnddddd"), + //INST(&V::SQRSHRUN_2, "SQRSHRUN, SQRSHRUN2", "0Q1011110IIIIiii100011nnnnnddddd"), + //INST(&V::UQSHRN_1, "UQSHRN, UQSHRN2", "011111110IIIIiii100101nnnnnddddd"), + //INST(&V::UQSHRN_2, "UQSHRN, UQSHRN2", "0Q1011110IIIIiii100101nnnnnddddd"), + //INST(&V::UQRSHRN_1, "UQRSHRN, UQRSHRN2", "011111110IIIIiii100111nnnnnddddd"), + //INST(&V::UQRSHRN_2, "UQRSHRN, UQRSHRN2", "0Q1011110IIIIiii100111nnnnnddddd"), + //INST(&V::UCVTF_fix_1, "UCVTF (vector, fixed-point)", "011111110IIIIiii111001nnnnnddddd"), + //INST(&V::UCVTF_fix_2, "UCVTF (vector, fixed-point)", "0Q1011110IIIIiii111001nnnnnddddd"), + //INST(&V::FCVTZU_fix_1, "FCVTZU (vector, fixed-point)", "011111110IIIIiii111111nnnnnddddd"), + //INST(&V::FCVTZU_fix_2, "FCVTZU (vector, fixed-point)", "0Q1011110IIIIiii111111nnnnnddddd"), + + // Data Processing - FP and SIMD - SIMD Scalar x indexed element + //INST(&V::SQDMLAL_elt_1, "SQDMLAL, SQDMLAL2 (by element)", "01011111zzLMmmmm0011H0nnnnnddddd"), + //INST(&V::SQDMLAL_elt_2, "SQDMLAL, SQDMLAL2 (by element)", "0Q001111zzLMmmmm0011H0nnnnnddddd"), + //INST(&V::SQDMLSL_elt_1, "SQDMLSL, SQDMLSL2 (by element)", "01011111zzLMmmmm0111H0nnnnnddddd"), + //INST(&V::SQDMLSL_elt_2, "SQDMLSL, SQDMLSL2 (by element)", "0Q001111zzLMmmmm0111H0nnnnnddddd"), + //INST(&V::SQDMULL_elt_1, "SQDMULL, SQDMULL2 (by element)", "01011111zzLMmmmm1011H0nnnnnddddd"), + //INST(&V::SQDMULL_elt_2, "SQDMULL, SQDMULL2 (by element)", "0Q001111zzLMmmmm1011H0nnnnnddddd"), + //INST(&V::SQDMULH_elt_1, "SQDMULH (by element)", "01011111zzLMmmmm1100H0nnnnnddddd"), + //INST(&V::SQDMULH_elt_2, "SQDMULH (by element)", "0Q001111zzLMmmmm1100H0nnnnnddddd"), + //INST(&V::SQRDMULH_elt_1, "SQRDMULH (by element)", "01011111zzLMmmmm1101H0nnnnnddddd"), + //INST(&V::SQRDMULH_elt_2, "SQRDMULH (by element)", "0Q001111zzLMmmmm1101H0nnnnnddddd"), + //INST(&V::FMLA_elt_1, "FMLA (by element)", "0101111100LMmmmm0001H0nnnnnddddd"), + //INST(&V::FMLA_elt_2, "FMLA (by element)", "010111111zLMmmmm0001H0nnnnnddddd"), + //INST(&V::FMLA_elt_3, "FMLA (by element)", "0Q00111100LMmmmm0001H0nnnnnddddd"), + //INST(&V::FMLA_elt_4, "FMLA (by element)", "0Q0011111zLMmmmm0001H0nnnnnddddd"), + //INST(&V::FMLS_elt_1, "FMLS (by element)", "0101111100LMmmmm0101H0nnnnnddddd"), + //INST(&V::FMLS_elt_2, "FMLS (by element)", "010111111zLMmmmm0101H0nnnnnddddd"), + //INST(&V::FMLS_elt_3, "FMLS (by element)", "0Q00111100LMmmmm0101H0nnnnnddddd"), + //INST(&V::FMLS_elt_4, "FMLS (by element)", "0Q0011111zLMmmmm0101H0nnnnnddddd"), + //INST(&V::FMUL_elt_1, "FMUL (by element)", "0101111100LMmmmm1001H0nnnnnddddd"), + //INST(&V::FMUL_elt_2, "FMUL (by element)", "010111111zLMmmmm1001H0nnnnnddddd"), + //INST(&V::FMUL_elt_3, "FMUL (by element)", "0Q00111100LMmmmm1001H0nnnnnddddd"), + //INST(&V::FMUL_elt_4, "FMUL (by element)", "0Q0011111zLMmmmm1001H0nnnnnddddd"), + //INST(&V::SQRDMLAH_elt_1, "SQRDMLAH (by element)", "01111111zzLMmmmm1101H0nnnnnddddd"), + //INST(&V::SQRDMLAH_elt_2, "SQRDMLAH (by element)", "0Q101111zzLMmmmm1101H0nnnnnddddd"), + //INST(&V::SQRDMLSH_elt_1, "SQRDMLSH (by element)", "01111111zzLMmmmm1111H0nnnnnddddd"), + //INST(&V::SQRDMLSH_elt_2, "SQRDMLSH (by element)", "0Q101111zzLMmmmm1111H0nnnnnddddd"), + //INST(&V::FMULX_elt_1, "FMULX (by element)", "0111111100LMmmmm1001H0nnnnnddddd"), + //INST(&V::FMULX_elt_2, "FMULX (by element)", "011111111zLMmmmm1001H0nnnnnddddd"), + //INST(&V::FMULX_elt_3, "FMULX (by element)", "0Q10111100LMmmmm1001H0nnnnnddddd"), + //INST(&V::FMULX_elt_4, "FMULX (by element)", "0Q1011111zLMmmmm1001H0nnnnnddddd"), + + // Data Processing - FP and SIMD - SIMD Table Lookup + //INST(&V::TBL, "TBL", "0Q001110000mmmmm0LL000nnnnnddddd"), + //INST(&V::TBX, "TBX", "0Q001110000mmmmm0LL100nnnnnddddd"), + + // Data Processing - FP and SIMD - SIMD Permute + //INST(&V::UZP1, "UZP1", "0Q001110zz0mmmmm000110nnnnnddddd"), + //INST(&V::TRN1, "TRN1", "0Q001110zz0mmmmm001010nnnnnddddd"), + //INST(&V::ZIP1, "ZIP1", "0Q001110zz0mmmmm001110nnnnnddddd"), + //INST(&V::UZP2, "UZP2", "0Q001110zz0mmmmm010110nnnnnddddd"), + //INST(&V::TRN2, "TRN2", "0Q001110zz0mmmmm011010nnnnnddddd"), + //INST(&V::ZIP2, "ZIP2", "0Q001110zz0mmmmm011110nnnnnddddd"), + + // Data Processing - FP and SIMD - SIMD Extract + //INST(&V::EXT, "EXT", "0Q101110000mmmmm0iiii0nnnnnddddd"), + + // Data Processing - FP and SIMD - SIMD Copy + //INST(&V::DUP_gen, "DUP (general)", "0Q001110000iiiii000011nnnnnddddd"), + //INST(&V::SMOV, "SMOV", "0Q001110000iiiii001011nnnnnddddd"), + //INST(&V::UMOV, "UMOV", "0Q001110000iiiii001111nnnnnddddd"), + //INST(&V::INS_gen, "INS (general)", "01001110000iiiii000111nnnnnddddd"), + //INST(&V::INS_elt, "INS (element)", "01101110000iiiii0iiii1nnnnnddddd"), + + // Data Processing - FP and SIMD - SIMD Three same + //INST(&V::FMAXNM_1, "FMAXNM (vector)", "0Q001110010mmmmm000001nnnnnddddd"), + //INST(&V::FMAXNM_2, "FMAXNM (vector)", "0Q0011100z1mmmmm110001nnnnnddddd"), + //INST(&V::FMLA_vec_1, "FMLA (vector)", "0Q001110010mmmmm000011nnnnnddddd"), + //INST(&V::FMLA_vec_2, "FMLA (vector)", "0Q0011100z1mmmmm110011nnnnnddddd"), + //INST(&V::FADD_1, "FADD (vector)", "0Q001110010mmmmm000101nnnnnddddd"), + //INST(&V::FADD_2, "FADD (vector)", "0Q0011100z1mmmmm110101nnnnnddddd"), + //INST(&V::FMAX_1, "FMAX (vector)", "0Q001110010mmmmm001101nnnnnddddd"), + //INST(&V::FMAX_2, "FMAX (vector)", "0Q0011100z1mmmmm111101nnnnnddddd"), + //INST(&V::FMINNM_1, "FMINNM (vector)", "0Q001110110mmmmm000001nnnnnddddd"), + //INST(&V::FMINNM_2, "FMINNM (vector)", "0Q0011101z1mmmmm110001nnnnnddddd"), + //INST(&V::FMLS_vec_1, "FMLS (vector)", "0Q001110110mmmmm000011nnnnnddddd"), + //INST(&V::FMLS_vec_2, "FMLS (vector)", "0Q0011101z1mmmmm110011nnnnnddddd"), + //INST(&V::FSUB_1, "FSUB (vector)", "0Q001110110mmmmm000101nnnnnddddd"), + //INST(&V::FSUB_2, "FSUB (vector)", "0Q0011101z1mmmmm110101nnnnnddddd"), + //INST(&V::FMIN_1, "FMIN (vector)", "0Q001110110mmmmm001101nnnnnddddd"), + //INST(&V::FMIN_2, "FMIN (vector)", "0Q0011101z1mmmmm111101nnnnnddddd"), + //INST(&V::FMAXNMP_vec_1, "FMAXNMP (vector)", "0Q101110010mmmmm000001nnnnnddddd"), + //INST(&V::FMAXNMP_vec_2, "FMAXNMP (vector)", "0Q1011100z1mmmmm110001nnnnnddddd"), + //INST(&V::FADDP_vec_1, "FADDP (vector)", "0Q101110010mmmmm000101nnnnnddddd"), + //INST(&V::FADDP_vec_2, "FADDP (vector)", "0Q1011100z1mmmmm110101nnnnnddddd"), + //INST(&V::FMUL_vec_1, "FMUL (vector)", "0Q101110010mmmmm000111nnnnnddddd"), + //INST(&V::FMUL_vec_2, "FMUL (vector)", "0Q1011100z1mmmmm110111nnnnnddddd"), + //INST(&V::FMAXP_vec_1, "FMAXP (vector)", "0Q101110010mmmmm001101nnnnnddddd"), + //INST(&V::FMAXP_vec_2, "FMAXP (vector)", "0Q1011100z1mmmmm111101nnnnnddddd"), + //INST(&V::FDIV_1, "FDIV (vector)", "0Q101110010mmmmm001111nnnnnddddd"), + //INST(&V::FDIV_2, "FDIV (vector)", "0Q1011100z1mmmmm111111nnnnnddddd"), + //INST(&V::FMINNMP_vec_1, "FMINNMP (vector)", "0Q101110110mmmmm000001nnnnnddddd"), + //INST(&V::FMINNMP_vec_2, "FMINNMP (vector)", "0Q1011101z1mmmmm110001nnnnnddddd"), + //INST(&V::FMINP_vec_1, "FMINP (vector)", "0Q101110110mmmmm001101nnnnnddddd"), + //INST(&V::FMINP_vec_2, "FMINP (vector)", "0Q1011101z1mmmmm111101nnnnnddddd"), + + // Data Processing - FP and SIMD - SIMD Two-register misc + //INST(&V::FRINTN_1, "FRINTN (vector)", "0Q00111001111001100010nnnnnddddd"), + //INST(&V::FRINTN_2, "FRINTN (vector)", "0Q0011100z100001100010nnnnnddddd"), + //INST(&V::FRINTM_1, "FRINTM (vector)", "0Q00111001111001100110nnnnnddddd"), + //INST(&V::FRINTM_2, "FRINTM (vector)", "0Q0011100z100001100110nnnnnddddd"), + //INST(&V::FABS_1, "FABS (vector)", "0Q00111011111000111110nnnnnddddd"), + //INST(&V::FABS_2, "FABS (vector)", "0Q0011101z100000111110nnnnnddddd"), + //INST(&V::FRINTP_1, "FRINTP (vector)", "0Q00111011111001100010nnnnnddddd"), + //INST(&V::FRINTP_2, "FRINTP (vector)", "0Q0011101z100001100010nnnnnddddd"), + //INST(&V::FRINTZ_1, "FRINTZ (vector)", "0Q00111011111001100110nnnnnddddd"), + //INST(&V::FRINTZ_2, "FRINTZ (vector)", "0Q0011101z100001100110nnnnnddddd"), + //INST(&V::FRINTA_1, "FRINTA (vector)", "0Q10111001111001100010nnnnnddddd"), + //INST(&V::FRINTA_2, "FRINTA (vector)", "0Q1011100z100001100010nnnnnddddd"), + //INST(&V::FRINTX_1, "FRINTX (vector)", "0Q10111001111001100110nnnnnddddd"), + //INST(&V::FRINTX_2, "FRINTX (vector)", "0Q1011100z100001100110nnnnnddddd"), + //INST(&V::FNEG_1, "FNEG (vector)", "0Q10111011111000111110nnnnnddddd"), + //INST(&V::FNEG_2, "FNEG (vector)", "0Q1011101z100000111110nnnnnddddd"), + //INST(&V::FRINTI_1, "FRINTI (vector)", "0Q10111011111001100110nnnnnddddd"), + //INST(&V::FRINTI_2, "FRINTI (vector)", "0Q1011101z100001100110nnnnnddddd"), + //INST(&V::FSQRT_1, "FSQRT (vector)", "0Q10111011111001111110nnnnnddddd"), + //INST(&V::FSQRT_2, "FSQRT (vector)", "0Q1011101z100001111110nnnnnddddd"), + + // Data Processing - FP and SIMD - SIMD Three same extra + //INST(&V::SDOT_vec, "SDOT (vector)", "0Q001110zz0mmmmm100101nnnnnddddd"), + //INST(&V::UDOT_vec, "UDOT (vector)", "0Q101110zz0mmmmm100101nnnnnddddd"), + //INST(&V::FCMLA_vec, "FCMLA", "0Q101110zz0mmmmm110rr1nnnnnddddd"), + //INST(&V::FCADD_vec, "FCADD", "0Q101110zz0mmmmm111r01nnnnnddddd"), + + // Data Processing - FP and SIMD - SIMD Two register misc + //INST(&V::REV64_asimd, "REV64", "0Q001110zz100000000010nnnnnddddd"), + //INST(&V::REV16_asimd, "REV16 (vector)", "0Q001110zz100000000110nnnnnddddd"), + //INST(&V::SADDLP, "SADDLP", "0Q001110zz100000001010nnnnnddddd"), + //INST(&V::CLS_asimd, "CLS (vector)", "0Q001110zz100000010010nnnnnddddd"), + //INST(&V::CNT, "CNT", "0Q001110zz100000010110nnnnnddddd"), + //INST(&V::SADALP, "SADALP", "0Q001110zz100000011010nnnnnddddd"), + //INST(&V::XTN, "XTN, XTN2", "0Q001110zz100001001010nnnnnddddd"), + //INST(&V::FCVTN, "FCVTN, FCVTN2", "0Q0011100z100001011010nnnnnddddd"), + //INST(&V::FCVTL, "FCVTL, FCVTL2", "0Q0011100z100001011110nnnnnddddd"), + //INST(&V::URECPE, "URECPE", "0Q0011101z100001110010nnnnnddddd"), + //INST(&V::REV32_asimd, "REV32 (vector)", "0Q101110zz100000000010nnnnnddddd"), + //INST(&V::UADDLP, "UADDLP", "0Q101110zz100000001010nnnnnddddd"), + //INST(&V::CLZ_asimd, "CLZ (vector)", "0Q101110zz100000010010nnnnnddddd"), + //INST(&V::UADALP, "UADALP", "0Q101110zz100000011010nnnnnddddd"), + //INST(&V::SHLL, "SHLL, SHLL2", "0Q101110zz100001001110nnnnnddddd"), + //INST(&V::NOT, "NOT", "0Q10111000100000010110nnnnnddddd"), + //INST(&V::RBIT_asimd, "RBIT (vector)", "0Q10111001100000010110nnnnnddddd"), + //INST(&V::URSQRTE, "URSQRTE", "0Q1011101z100001110010nnnnnddddd"), + + // Data Processing - FP and SIMD - SIMD across lanes + //INST(&V::SADDLV, "SADDLV", "0Q001110zz110000001110nnnnnddddd"), + //INST(&V::SMAXV, "SMAXV", "0Q001110zz110000101010nnnnnddddd"), + //INST(&V::SMINV, "SMINV", "0Q001110zz110001101010nnnnnddddd"), + //INST(&V::ADDV, "ADDV", "0Q001110zz110001101110nnnnnddddd"), + //INST(&V::FMAXNMV_1, "FMAXNMV", "0Q00111000110000110010nnnnnddddd"), + //INST(&V::FMAXNMV_2, "FMAXNMV", "0Q1011100z110000110010nnnnnddddd"), + //INST(&V::FMAXV_1, "FMAXV", "0Q00111000110000111110nnnnnddddd"), + //INST(&V::FMAXV_2, "FMAXV", "0Q1011100z110000111110nnnnnddddd"), + //INST(&V::FMINNMV_1, "FMINNMV", "0Q00111010110000110010nnnnnddddd"), + //INST(&V::FMINNMV_2, "FMINNMV", "0Q1011101z110000110010nnnnnddddd"), + //INST(&V::FMINV_1, "FMINV", "0Q00111010110000111110nnnnnddddd"), + //INST(&V::FMINV_2, "FMINV", "0Q1011101z110000111110nnnnnddddd"), + //INST(&V::UADDLV, "UADDLV", "0Q101110zz110000001110nnnnnddddd"), + //INST(&V::UMAXV, "UMAXV", "0Q101110zz110000101010nnnnnddddd"), + //INST(&V::UMINV, "UMINV", "0Q101110zz110001101010nnnnnddddd"), + + // Data Processing - FP and SIMD - SIMD three different + //INST(&V::SADDL, "SADDL, SADDL2", "0Q001110zz1mmmmm000000nnnnnddddd"), + //INST(&V::SADDW, "SADDW, SADDW2", "0Q001110zz1mmmmm000100nnnnnddddd"), + //INST(&V::SSUBL, "SSUBL, SSUBL2", "0Q001110zz1mmmmm001000nnnnnddddd"), + //INST(&V::SSUBW, "SSUBW, SSUBW2", "0Q001110zz1mmmmm001100nnnnnddddd"), + //INST(&V::ADDHN, "ADDHN, ADDHN2", "0Q001110zz1mmmmm010000nnnnnddddd"), + //INST(&V::SABAL, "SABAL, SABAL2", "0Q001110zz1mmmmm010100nnnnnddddd"), + //INST(&V::SUBHN, "SUBHN, SUBHN2", "0Q001110zz1mmmmm011000nnnnnddddd"), + //INST(&V::SABDL, "SABDL, SABDL2", "0Q001110zz1mmmmm011100nnnnnddddd"), + //INST(&V::SMLAL_vec, "SMLAL, SMLAL2 (vector)", "0Q001110zz1mmmmm100000nnnnnddddd"), + //INST(&V::SMLSL_vec, "SMLSL, SMLSL2 (vector)", "0Q001110zz1mmmmm101000nnnnnddddd"), + //INST(&V::SMULL_vec, "SMULL, SMULL2 (vector)", "0Q001110zz1mmmmm110000nnnnnddddd"), + //INST(&V::PMULL, "PMULL, PMULL2", "0Q001110zz1mmmmm111000nnnnnddddd"), + //INST(&V::UADDL, "UADDL, UADDL2", "0Q101110zz1mmmmm000000nnnnnddddd"), + //INST(&V::UADDW, "UADDW, UADDW2", "0Q101110zz1mmmmm000100nnnnnddddd"), + //INST(&V::USUBL, "USUBL, USUBL2", "0Q101110zz1mmmmm001000nnnnnddddd"), + //INST(&V::USUBW, "USUBW, USUBW2", "0Q101110zz1mmmmm001100nnnnnddddd"), + //INST(&V::RADDHN, "RADDHN, RADDHN2", "0Q101110zz1mmmmm010000nnnnnddddd"), + //INST(&V::UABAL, "UABAL, UABAL2", "0Q101110zz1mmmmm010100nnnnnddddd"), + //INST(&V::RSUBHN, "RSUBHN, RSUBHN2", "0Q101110zz1mmmmm011000nnnnnddddd"), + //INST(&V::UABDL, "UABDL, UABDL2", "0Q101110zz1mmmmm011100nnnnnddddd"), + //INST(&V::UMLAL_vec, "UMLAL, UMLAL2 (vector)", "0Q101110zz1mmmmm100000nnnnnddddd"), + //INST(&V::UMLSL_vec, "UMLSL, UMLSL2 (vector)", "0Q101110zz1mmmmm101000nnnnnddddd"), + //INST(&V::UMULL_vec, "UMULL, UMULL2 (vector)", "0Q101110zz1mmmmm110000nnnnnddddd"), + + // Data Processing - FP and SIMD - SIMD three same + //INST(&V::SHADD, "SHADD", "0Q001110zz1mmmmm000001nnnnnddddd"), + //INST(&V::SRHADD, "SRHADD", "0Q001110zz1mmmmm000101nnnnnddddd"), + //INST(&V::SHSUB, "SHSUB", "0Q001110zz1mmmmm001001nnnnnddddd"), + //INST(&V::SMAX, "SMAX", "0Q001110zz1mmmmm011001nnnnnddddd"), + //INST(&V::SMIN, "SMIN", "0Q001110zz1mmmmm011011nnnnnddddd"), + //INST(&V::SABD, "SABD", "0Q001110zz1mmmmm011101nnnnnddddd"), + //INST(&V::SABA, "SABA", "0Q001110zz1mmmmm011111nnnnnddddd"), + //INST(&V::MLA_vec, "MLA (vector)", "0Q001110zz1mmmmm100101nnnnnddddd"), + //INST(&V::MUL_vec, "MUL (vector)", "0Q001110zz1mmmmm100111nnnnnddddd"), + //INST(&V::SMAXP, "SMAXP", "0Q001110zz1mmmmm101001nnnnnddddd"), + //INST(&V::SMINP, "SMINP", "0Q001110zz1mmmmm101011nnnnnddddd"), + //INST(&V::ADDP_vec, "ADDP (vector)", "0Q001110zz1mmmmm101111nnnnnddddd"), + //INST(&V::FMLAL_vec_1, "FMLAL, FMLAL2 (vector)", "0Q0011100z1mmmmm111011nnnnnddddd"), + //INST(&V::FMLAL_vec_2, "FMLAL, FMLAL2 (vector)", "0Q1011100z1mmmmm110011nnnnnddddd"), + //INST(&V::AND_asimd, "AND (vector)", "0Q001110001mmmmm000111nnnnnddddd"), + //INST(&V::BIC_asimd_reg, "BIC (vector, register)", "0Q001110011mmmmm000111nnnnnddddd"), + //INST(&V::FMLSL_vec_1, "FMLSL, FMLSL2 (vector)", "0Q0011101z1mmmmm111011nnnnnddddd"), + //INST(&V::FMLSL_vec_2, "FMLSL, FMLSL2 (vector)", "0Q1011101z1mmmmm110011nnnnnddddd"), + //INST(&V::ORR_asimd_reg, "ORR (vector, register)", "0Q001110101mmmmm000111nnnnnddddd"), + //INST(&V::ORN_asimd, "ORN (vector)", "0Q001110111mmmmm000111nnnnnddddd"), + //INST(&V::UHADD, "UHADD", "0Q101110zz1mmmmm000001nnnnnddddd"), + //INST(&V::URHADD, "URHADD", "0Q101110zz1mmmmm000101nnnnnddddd"), + //INST(&V::UHSUB, "UHSUB", "0Q101110zz1mmmmm001001nnnnnddddd"), + //INST(&V::UMAX, "UMAX", "0Q101110zz1mmmmm011001nnnnnddddd"), + //INST(&V::UMIN, "UMIN", "0Q101110zz1mmmmm011011nnnnnddddd"), + //INST(&V::UABD, "UABD", "0Q101110zz1mmmmm011101nnnnnddddd"), + //INST(&V::UABA, "UABA", "0Q101110zz1mmmmm011111nnnnnddddd"), + //INST(&V::MLS_vec, "MLS (vector)", "0Q101110zz1mmmmm100101nnnnnddddd"), + //INST(&V::PMUL, "PMUL", "0Q101110zz1mmmmm100111nnnnnddddd"), + //INST(&V::UMAXP, "UMAXP", "0Q101110zz1mmmmm101001nnnnnddddd"), + //INST(&V::UMINP, "UMINP", "0Q101110zz1mmmmm101011nnnnnddddd"), + //INST(&V::EOR_asimd, "EOR (vector)", "0Q101110001mmmmm000111nnnnnddddd"), + //INST(&V::BSL, "BSL", "0Q101110011mmmmm000111nnnnnddddd"), + //INST(&V::BIT, "BIT", "0Q101110101mmmmm000111nnnnnddddd"), + //INST(&V::BIF, "BIF", "0Q101110111mmmmm000111nnnnnddddd"), + + // Data Processing - FP and SIMD - SIMD modified immediate + //INST(&V::MOVI, "MOVI", "0Qo0111100000abcmmmm01defghddddd"), + //INST(&V::ORR_asimd_imm, "ORR (vector, immediate)", "0Q00111100000abc---101defghddddd"), + //INST(&V::FMOV_1, "FMOV (vector, immediate)", "0Q00111100000abc111111defghddddd"), + //INST(&V::FMOV_2, "FMOV (vector, immediate)", "0Qo0111100000abc111101defghddddd"), + //INST(&V::MVNI, "MVNI", "0Q10111100000abcmmmm01defghddddd"), + //INST(&V::BIC_imm, "BIC (vector, immediate)", "0Q10111100000abc---101defghddddd"), + + // Data Processing - FP and SIMD - SIMD Shfit by immediate + //INST(&V::SHRN, "SHRN, SHRN2", "0Q0011110IIIIiii100001nnnnnddddd"), + //INST(&V::RSHRN, "RSHRN, RSHRN2", "0Q0011110IIIIiii100011nnnnnddddd"), + //INST(&V::SSHLL, "SSHLL, SSHLL2", "0Q0011110IIIIiii101001nnnnnddddd"), + //INST(&V::USHLL, "USHLL, USHLL2", "0Q1011110IIIIiii101001nnnnnddddd"), + + // Data Processing - FP and SIMD - SIMD x indexed element + //INST(&V::SMLAL_elt, "SMLAL, SMLAL2 (by element)", "0Q001111zzLMmmmm0010H0nnnnnddddd"), + //INST(&V::SMLSL_elt, "SMLSL, SMLSL2 (by element)", "0Q001111zzLMmmmm0110H0nnnnnddddd"), + //INST(&V::MUL_elt, "MUL (by element)", "0Q001111zzLMmmmm1000H0nnnnnddddd"), + //INST(&V::SMULL_elt, "SMULL, SMULL2 (by element)", "0Q001111zzLMmmmm1010H0nnnnnddddd"), + //INST(&V::SDOT_elt, "SDOT (by element)", "0Q001111zzLMmmmm1110H0nnnnnddddd"), + //INST(&V::FMLAL_elt_1, "FMLAL, FMLAL2 (by element)", "0Q0011111zLMmmmm0000H0nnnnnddddd"), + //INST(&V::FMLAL_elt_2, "FMLAL, FMLAL2 (by element)", "0Q1011111zLMmmmm1000H0nnnnnddddd"), + //INST(&V::FMLSL_elt_1, "FMLSL, FMLSL2 (by element)", "0Q0011111zLMmmmm0100H0nnnnnddddd"), + //INST(&V::FMLSL_elt_2, "FMLSL, FMLSL2 (by element)", "0Q1011111zLMmmmm1100H0nnnnnddddd"), + //INST(&V::MLA_elt, "MLA (by element)", "0Q101111zzLMmmmm0000H0nnnnnddddd"), + //INST(&V::UMLAL_elt, "UMLAL, UMLAL2 (by element)", "0Q101111zzLMmmmm0010H0nnnnnddddd"), + //INST(&V::MLS_elt, "MLS (by element)", "0Q101111zzLMmmmm0100H0nnnnnddddd"), + //INST(&V::UMLSL_elt, "UMLSL, UMLSL2 (by element)", "0Q101111zzLMmmmm0110H0nnnnnddddd"), + //INST(&V::UMULL_elt, "UMULL, UMULL2 (by element)", "0Q101111zzLMmmmm1010H0nnnnnddddd"), + //INST(&V::UDOT_elt, "UDOT (by element)", "0Q101111zzLMmmmm1110H0nnnnnddddd"), + //INST(&V::FCMLA_elt, "FCMLA (by element)", "0Q101111zzLMmmmm0rr1H0nnnnnddddd"), + + // Data Processing - FP and SIMD - Cryptographic three register + //INST(&V::SM3TT1A, "SM3TT1A", "11001110010mmmmm10ii00nnnnnddddd"), + //INST(&V::SM3TT1B, "SM3TT1B", "11001110010mmmmm10ii01nnnnnddddd"), + //INST(&V::SM3TT2A, "SM3TT2A", "11001110010mmmmm10ii10nnnnnddddd"), + //INST(&V::SM3TT2B, "SM3TT2B", "11001110010mmmmm10ii11nnnnnddddd"), + + // Data Processing - FP and SIMD - SHA512 three register + //INST(&V::SHA512H, "SHA512H", "11001110011mmmmm100000nnnnnddddd"), + //INST(&V::SHA512H2, "SHA512H2", "11001110011mmmmm100001nnnnnddddd"), + //INST(&V::SHA512SU1, "SHA512SU1", "11001110011mmmmm100010nnnnnddddd"), + //INST(&V::RAX1, "RAX1", "11001110011mmmmm100011nnnnnddddd"), + //INST(&V::SM3PARTW1, "SM3PARTW1", "11001110011mmmmm110000nnnnnddddd"), + //INST(&V::SM3PARTW2, "SM3PARTW2", "11001110011mmmmm110001nnnnnddddd"), + //INST(&V::SM4EKEY, "SM4EKEY", "11001110011mmmmm110010nnnnnddddd"), + + // Data Processing - FP and SIMD - Cryptographic four register + //INST(&V::EOR3, "EOR3", "11001110000mmmmm0aaaaannnnnddddd"), + //INST(&V::BCAX, "BCAX", "11001110001mmmmm0aaaaannnnnddddd"), + //INST(&V::SM3SS1, "SM3SS1", "11001110010mmmmm0aaaaannnnnddddd"), + + // Data Processing - FP and SIMD - SHA512 two register + //INST(&V::SHA512SU0, "SHA512SU0", "1100111011000000100000nnnnnddddd"), + //INST(&V::SM4E, "SM4E", "1100111011000000100001nnnnnddddd"), + + // Data Processing - FP and SIMD - Conversion between floating point and fixed point + //INST(&V::SCVTF_float_fix, "SCVTF (scalar, fixed-point)", "z0011110yy000010ppppppnnnnnddddd"), + //INST(&V::UCVTF_float_fix, "UCVTF (scalar, fixed-point)", "z0011110yy000011ppppppnnnnnddddd"), + //INST(&V::FCVTZS_float_fix, "FCVTZS (scalar, fixed-point)", "z0011110yy011000ppppppnnnnnddddd"), + //INST(&V::FCVTZU_float_fix, "FCVTZU (scalar, fixed-point)", "z0011110yy011001ppppppnnnnnddddd"), + + // Data Processing - FP and SIMD - Conversion between floating point and integer + //INST(&V::FCVTNS_float, "FCVTNS (scalar)", "z0011110yy100000000000nnnnnddddd"), + //INST(&V::FCVTNU_float, "FCVTNU (scalar)", "z0011110yy100001000000nnnnnddddd"), + //INST(&V::SCVTF_float_int, "SCVTF (scalar, integer)", "z0011110yy100010000000nnnnnddddd"), + //INST(&V::UCVTF_float_int, "UCVTF (scalar, integer)", "z0011110yy100011000000nnnnnddddd"), + //INST(&V::FCVTAS_float, "FCVTAS (scalar)", "z0011110yy100100000000nnnnnddddd"), + //INST(&V::FCVTAU_float, "FCVTAU (scalar)", "z0011110yy100101000000nnnnnddddd"), + //INST(&V::FMOV_float_gen, "FMOV (general)", "z0011110yy10-11-000000nnnnnddddd"), + //INST(&V::FCVTPS_float, "FCVTPS (scalar)", "z0011110yy101000000000nnnnnddddd"), + //INST(&V::FCVTPU_float, "FCVTPU (scalar)", "z0011110yy101001000000nnnnnddddd"), + //INST(&V::FCVTMS_float, "FCVTMS (scalar)", "z0011110yy110000000000nnnnnddddd"), + //INST(&V::FCVTMU_float, "FCVTMU (scalar)", "z0011110yy110001000000nnnnnddddd"), + //INST(&V::FCVTZS_float_int, "FCVTZS (scalar, integer)", "z0011110yy111000000000nnnnnddddd"), + //INST(&V::FCVTZU_float_int, "FCVTZU (scalar, integer)", "z0011110yy111001000000nnnnnddddd"), + //INST(&V::FJCVTZS, "FJCVTZS", "0001111001111110000000nnnnnddddd"), + + // Data Processing - FP and SIMD - Floating point data processing + //INST(&V::FMOV_float, "FMOV (register)", "00011110yy100000010000nnnnnddddd"), + //INST(&V::FABS_float, "FABS (scalar)", "00011110yy100000110000nnnnnddddd"), + //INST(&V::FNEG_float, "FNEG (scalar)", "00011110yy100001010000nnnnnddddd"), + //INST(&V::FSQRT_float, "FSQRT (scalar)", "00011110yy100001110000nnnnnddddd"), + //INST(&V::FCVT_float, "FCVT", "00011110yy10001oo10000nnnnnddddd"), + //INST(&V::FRINTN_float, "FRINTN (scalar)", "00011110yy100100010000nnnnnddddd"), + //INST(&V::FRINTP_float, "FRINTP (scalar)", "00011110yy100100110000nnnnnddddd"), + //INST(&V::FRINTM_float, "FRINTM (scalar)", "00011110yy100101010000nnnnnddddd"), + //INST(&V::FRINTZ_float, "FRINTZ (scalar)", "00011110yy100101110000nnnnnddddd"), + //INST(&V::FRINTA_float, "FRINTA (scalar)", "00011110yy100110010000nnnnnddddd"), + //INST(&V::FRINTX_float, "FRINTX (scalar)", "00011110yy100111010000nnnnnddddd"), + //INST(&V::FRINTI_float, "FRINTI (scalar)", "00011110yy100111110000nnnnnddddd"), + + // Data Processing - FP and SIMD - Floating point compare + //INST(&V::FCMP_float, "FCMP", "00011110yy1mmmmm001000nnnnn0-000"), + //INST(&V::FCMPE_float, "FCMPE", "00011110yy1mmmmm001000nnnnn1-000"), + + // Data Processing - FP and SIMD - Floating point immediate + //INST(&V::FMOV_float_imm, "FMOV (scalar, immediate)", "00011110yy1iiiiiiii10000000ddddd"), + + // Data Processing - FP and SIMD - Floating point conditional compare + //INST(&V::FCCMP_float, "FCCMP", "00011110yy1mmmmmcccc01nnnnn0ffff"), + //INST(&V::FCCMPE_float, "FCCMPE", "00011110yy1mmmmmcccc01nnnnn1ffff"), + + // Data Processing - FP and SIMD - Floating point data processing two register + //INST(&V::FMUL_float, "FMUL (scalar)", "00011110yy1mmmmm000010nnnnnddddd"), + //INST(&V::FDIV_float, "FDIV (scalar)", "00011110yy1mmmmm000110nnnnnddddd"), + //INST(&V::FADD_float, "FADD (scalar)", "00011110yy1mmmmm001010nnnnnddddd"), + //INST(&V::FSUB_float, "FSUB (scalar)", "00011110yy1mmmmm001110nnnnnddddd"), + //INST(&V::FMAX_float, "FMAX (scalar)", "00011110yy1mmmmm010010nnnnnddddd"), + //INST(&V::FMIN_float, "FMIN (scalar)", "00011110yy1mmmmm010110nnnnnddddd"), + //INST(&V::FMAXNM_float, "FMAXNM (scalar)", "00011110yy1mmmmm011010nnnnnddddd"), + //INST(&V::FMINNM_float, "FMINNM (scalar)", "00011110yy1mmmmm011110nnnnnddddd"), + //INST(&V::FNMUL_float, "FNMUL (scalar)", "00011110yy1mmmmm100010nnnnnddddd"), + + // Data Processing - FP and SIMD - Floating point conditional select + //INST(&V::FCSEL_float, "FCSEL", "00011110yy1mmmmmcccc11nnnnnddddd"), + + // Data Processing - FP and SIMD - Floating point data processing three register + //INST(&V::FMADD_float, "FMADD", "00011111yy0mmmmm0aaaaannnnnddddd"), + //INST(&V::FMSUB_float, "FMSUB", "00011111yy0mmmmm1aaaaannnnnddddd"), + //INST(&V::FNMADD_float, "FNMADD", "00011111yy1mmmmm0aaaaannnnnddddd"), + //INST(&V::FNMSUB_float, "FNMSUB", "00011111yy1mmmmm1aaaaannnnnddddd"), + +#undef INST + + }; + + // If a matcher has more bits in its mask it is more specific, so it should come first. + std::stable_sort(table.begin(), table.end(), [](const auto& matcher1, const auto& matcher2) { + return Common::BitCount(matcher1.GetMask()) > Common::BitCount(matcher2.GetMask()); + }); + + return table; +} + +template +boost::optional&> Decode(u32 instruction) { + static const auto table = GetDecodeTable(); + + const auto matches_instruction = [instruction](const auto& matcher) { return matcher.Matches(instruction); }; + + auto iter = std::find_if(table.begin(), table.end(), matches_instruction); + return iter != table.end() ? boost::optional&>(*iter) : boost::none; +} + +} // namespace A64 +} // namespace Dynarmic diff --git a/src/frontend/A64/imm.h b/src/frontend/A64/imm.h new file mode 100644 index 00000000..81714e72 --- /dev/null +++ b/src/frontend/A64/imm.h @@ -0,0 +1,99 @@ +/* This file is part of the dynarmic project. + * Copyright (c) 2018 MerryMage + * This software may be used and distributed according to the terms of the GNU + * General Public License version 2 or any later version. + */ + +#pragma once + +#include "common/assert.h" +#include "common/bit_util.h" +#include "common/common_types.h" + +namespace Dynarmic { +namespace A64 { + +/** + * Imm represents an immediate value in an AArch64 instruction. + * Imm is used during translation as a typesafe way of passing around immediates of fixed sizes. + */ +template +class Imm { +public: + static constexpr size_t bit_size = bit_size_; + + explicit Imm(u32 value) : value(value) { + ASSERT_MSG((Common::Bits<0, bit_size-1>(value) == value), "More bits in value than expected"); + } + + template + T ZeroExtend() const { + static_assert(Common::BitSize() <= bit_size); + return value; + } + + template + T SignExtend() const { + static_assert(Common::BitSize() <= bit_size); + return static_cast(Common::SignExtend(value)); + } + + template + bool Bit() const { + static_assert(bit < bit_size); + return Common::Bit(value); + } + + bool operator==(const Imm& other) const { + return value == other.value; + } + + bool operator!=(const Imm& other) const { + return value != other.value; + } + +private: + static_assert(bit_size != 0, "Cannot have a zero-sized immediate"); + static_assert(bit_size <= 32, "Cannot have an immediate larger than the instruction size"); + + u32 value; +}; + +template +bool operator==(u32 a, const Imm& b) { + return Imm{a} == b; +} + +template +bool operator==(const Imm& a, u32 b) { + return Imm{b} == a; +} + +template +bool operator!=(u32 a, const Imm& b) { + return Imm{a} != b; +} + +template +bool operator!=(const Imm& a, u32 b) { + return Imm{b} != a; +} + +/** + * Concatentate immediates together. + * Left to right correpeonds to most significant imm to least significant imm. + * This is equivalent to a:b:...:z in ASL. + */ +template +auto concatenate(Imm first, Imm ...rest) -> Imm<(first_bit_size + ... + rest_bit_sizes)> { + if constexpr (sizeof...(rest) == 0) { + return first; + } else { + const auto concat_rest = concatenate(rest...); + const u32 value = (first.ZeroExtend() << concat_rest.bit_size) | concat_rest.ZeroExtend(); + return Imm<(first_bit_size + ... + rest_bit_sizes)>{value}; + } +} + +} // namespace A64 +} // namespace Dynarmic diff --git a/src/frontend/A64/location_descriptor.cpp b/src/frontend/A64/location_descriptor.cpp new file mode 100644 index 00000000..cbde1a5d --- /dev/null +++ b/src/frontend/A64/location_descriptor.cpp @@ -0,0 +1,21 @@ +/* This file is part of the dynarmic project. + * Copyright (c) 2016 MerryMage + * This software may be used and distributed according to the terms of the GNU + * General Public License version 2 or any later version. + */ + +#include +#include + +#include "frontend/A64/location_descriptor.h" + +namespace Dynarmic { +namespace A64 { + +std::ostream& operator<<(std::ostream& o, const LocationDescriptor& loc) { + o << fmt::format("{{{}, {}}}", loc.PC(), loc.FPCR().Value()); + return o; +} + +} // namespace A64 +} // namespace Dynarmic diff --git a/src/frontend/A64/location_descriptor.h b/src/frontend/A64/location_descriptor.h new file mode 100644 index 00000000..31a66e3f --- /dev/null +++ b/src/frontend/A64/location_descriptor.h @@ -0,0 +1,95 @@ +/* This file is part of the dynarmic project. + * Copyright (c) 2016 MerryMage + * This software may be used and distributed according to the terms of the GNU + * General Public License version 2 or any later version. + */ + +#pragma once + +#include +#include +#include + +#include "common/bit_util.h" +#include "common/common_types.h" +#include "frontend/A64/FPCR.h" +#include "frontend/ir/location_descriptor.h" + +namespace Dynarmic { +namespace A64 { + +/** + * LocationDescriptor describes the location of a basic block. + * The location is not solely based on the PC because other flags influence the way + * instructions should be translated. + */ +class LocationDescriptor { +public: + static constexpr u64 PC_MASK = 0x00FF'FFFF'FFFF'FFFFull; + static constexpr u32 FPCR_MASK = 0x07C0'0000; + + LocationDescriptor(u64 pc, FPCR fpcr) : pc(pc & PC_MASK), fpcr(fpcr.Value() & FPCR_MASK) {} + + explicit LocationDescriptor(const IR::LocationDescriptor& o) + : pc(o.Value() & PC_MASK), fpcr((o.Value() >> 37) & FPCR_MASK) {} + + u64 PC() const { return Common::SignExtend<56>(pc); } + FPCR FPCR() const { return fpcr; } + + bool operator == (const LocationDescriptor& o) const { + return std::tie(pc, fpcr) == std::tie(o.pc, o.fpcr); + } + + bool operator != (const LocationDescriptor& o) const { + return !operator==(o); + } + + LocationDescriptor SetPC(u32 new_pc) const { + return LocationDescriptor(new_pc, fpcr); + } + + LocationDescriptor AdvancePC(int amount) const { + return LocationDescriptor(static_cast(pc + amount), fpcr); + } + + u64 UniqueHash() const { + // This value MUST BE UNIQUE. + // This calculation has to match up with EmitTerminalPopRSBHint + u64 fpcr_u64 = static_cast(fpcr.Value()) << 37; + return pc | fpcr_u64; + } + + operator IR::LocationDescriptor() const { + return IR::LocationDescriptor{UniqueHash()}; + } + +private: + u64 pc; ///< Current program counter value. + A64::FPCR fpcr; ///< Floating point control register. +}; + +/** + * Provides a string representation of a LocationDescriptor. + * + * @param o Output stream + * @param descriptor The descriptor to get a string representation of + */ +std::ostream& operator<<(std::ostream& o, const LocationDescriptor& descriptor); + +} // namespace A64 +} // namespace Dynarmic + +namespace std { +template <> +struct less { + bool operator()(const Dynarmic::A64::LocationDescriptor& x, const Dynarmic::A64::LocationDescriptor& y) const { + return x.UniqueHash() < y.UniqueHash(); + } +}; +template <> +struct hash { + size_t operator()(const Dynarmic::A64::LocationDescriptor& x) const { + return std::hash()(x.UniqueHash()); + } +}; +} // namespace std diff --git a/src/frontend/A64/translate/impl/impl.h b/src/frontend/A64/translate/impl/impl.h new file mode 100644 index 00000000..663930ff --- /dev/null +++ b/src/frontend/A64/translate/impl/impl.h @@ -0,0 +1,1043 @@ +/* This file is part of the dynarmic project. + * Copyright (c) 2018 MerryMage + * This software may be used and distributed according to the terms of the GNU + * General Public License version 2 or any later version. + */ + +#pragma once + +#include "frontend/A64/imm.h" +#include "frontend/A64/ir_emitter.h" +#include "frontend/A64/location_descriptor.h" +#include "frontend/A64/types.h" + +namespace Dynarmic { +namespace A64 { + +struct TranslatorVisitor final { + using instruction_return_type = bool; + + explicit TranslatorVisitor(LocationDescriptor descriptor) : ir(descriptor) {} + + A64::IREmitter ir; + + bool InterpretThisInstruction(); + bool UnpredictableInstruction(); + + // Data processing - Immediate - PC relative addressing + bool ADR(Imm<2> immlo, Imm<19> immhi, Reg Rd); + bool ADRP(Imm<2> immlo, Imm<19> immhi, Reg Rd); + + // Data processing - Immediate - Add/Sub + bool ADD_imm(bool sf, Imm<2> shift, Imm<12> imm12, Reg Rn, Reg Rd); + bool ADDS_imm(bool sf, Imm<2> shift, Imm<12> imm12, Reg Rn, Reg Rd); + bool SUB_imm(bool sf, Imm<2> shift, Imm<12> imm12, Reg Rn, Reg Rd); + bool SUBS_imm(bool sf, Imm<2> shift, Imm<12> imm12, Reg Rn, Reg Rd); + + // Data processing - Immediate - Logical + bool AND_imm(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg Rn, Reg Rd); + bool ORR_imm(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg Rn, Reg Rd); + bool EOR_imm(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg Rn, Reg Rd); + bool ANDS_imm(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg Rn, Reg Rd); + + // Data processing - Immediate - Move Wide + bool MOVN(bool sf, Imm<2> hw, Imm<16> imm16, Reg Rd); + bool MOVZ(bool sf, Imm<2> hw, Imm<16> imm16, Reg Rd); + bool MOVK(bool sf, Imm<2> hw, Imm<16> imm16, Reg Rd); + + // Data processing - Immediate - Bitfield + bool SBFM(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg Rn, Reg Rd); + bool BFM(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg Rn, Reg Rd); + bool UBFM(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg Rn, Reg Rd); + + // Data processing - Immediate - Extract + bool EXTR(bool sf, bool N, Reg Rm, Imm<6> imms, Reg Rn, Reg Rd); + + // Conditional branch + bool B_cond(Imm<19> imm19, Cond cond); + + // Exception generation + bool SVC(Imm<16> imm16); + bool HVC(Imm<16> imm16); + bool SMC(Imm<16> imm16); + bool BRK(Imm<16> imm16); + bool HLT(Imm<16> imm16); + bool DCPS1(Imm<16> imm16); + bool DCPS2(Imm<16> imm16); + bool DCPS3(Imm<16> imm16); + + // System + bool MSR_imm(Imm<3> op1, Imm<4> CRm, Imm<3> op2); + bool HINT(Imm<4> CRm, Imm<3> op2); + bool NOP(); + bool YIELD(); + bool WFE(); + bool WFI(); + bool SEV(); + bool SEVL(); + bool XPAC_1(bool D, Reg Rd); + bool XPAC_2(); + bool PACIA_1(bool Z, Reg Rn, Reg Rd); + bool PACIA_2(); + bool PACIB_1(bool Z, Reg Rn, Reg Rd); + bool PACIB_2(); + bool AUTIA_1(bool Z, Reg Rn, Reg Rd); + bool AUTIA_2(); + bool AUTIB_1(bool Z, Reg Rn, Reg Rd); + bool AUTIB_2(); + bool ESB(); + bool PSB(); + bool CLREX(Imm<4> CRm); + bool DSB(Imm<4> CRm); + bool DMB(Imm<4> CRm); + bool ISB(Imm<4> CRm); + bool SYS(Imm<3> op1, Imm<4> CRn, Imm<4> CRm, Imm<3> op2, Reg Rt); + bool MSR_reg(bool o0, Imm<3> op1, Imm<4> CRn, Imm<4> CRm, Imm<3> op2, Reg Rt); + bool SYSL(Imm<3> op1, Imm<4> CRn, Imm<4> CRm, Imm<3> op2, Reg Rt); + bool MRS(bool o0, Imm<3> op1, Imm<4> CRn, Imm<4> CRm, Imm<3> op2, Reg Rt); + + // Unconditonal branch (Register) + bool BR(Reg Rn); + bool BRA(bool Z, bool M, Reg Rn, Reg Rm); + bool BLR(Reg Rn); + bool BLRA(bool Z, bool M, Reg Rn, Reg Rm); + bool RET(Reg Rn); + bool RETA(bool M); + bool ERET(); + bool ERETA(bool M); + bool DRPS(); + + // Unconditonal branch (immediate) + bool B_uncond(Imm<26> imm26); + bool BL(Imm<26> imm26); + + // Compare and branch (immediate) + bool CBZ(bool sf, Imm<19> imm19, Reg Rt); + bool CBNZ(bool sf, Imm<19> imm19, Reg Rt); + bool TBZ(Imm<1> b5, Imm<5> b40, Imm<14> imm14, Reg Rt); + bool TBNZ(Imm<1> b5, Imm<5> b40, Imm<14> imm14, Reg Rt); + + // Loads and stores - Advanced SIMD Load/Store multiple structures + bool ST4_mult_1(bool Q, Imm<2> size, Reg Rn, Reg Rt); + bool ST4_mult_2(bool Q, Reg Rm, Imm<2> size, Reg Rn, Reg Rt); + bool ST1_mult_1(bool Q, Imm<2> size, Reg Rn, Reg Rt); + bool ST1_mult_2(bool Q, Reg Rm, Imm<2> size, Reg Rn, Reg Rt); + bool ST3_mult_1(bool Q, Imm<2> size, Reg Rn, Reg Rt); + bool ST3_mult_2(bool Q, Reg Rm, Imm<2> size, Reg Rn, Reg Rt); + bool ST2_mult_1(bool Q, Imm<2> size, Reg Rn, Reg Rt); + bool ST2_mult_2(bool Q, Reg Rm, Imm<2> size, Reg Rn, Reg Rt); + bool LD4_mult_1(bool Q, Imm<2> size, Reg Rn, Reg Rt); + bool LD4_mult_2(bool Q, Reg Rm, Imm<2> size, Reg Rn, Reg Rt); + bool LD1_mult_1(bool Q, Imm<2> size, Reg Rn, Reg Rt); + bool LD1_mult_2(bool Q, Reg Rm, Imm<2> size, Reg Rn, Reg Rt); + bool LD3_mult_1(bool Q, Imm<2> size, Reg Rn, Reg Rt); + bool LD3_mult_2(bool Q, Reg Rm, Imm<2> size, Reg Rn, Reg Rt); + bool LD2_mult_1(bool Q, Imm<2> size, Reg Rn, Reg Rt); + bool LD2_mult_2(bool Q, Reg Rm, Imm<2> size, Reg Rn, Reg Rt); + + // Loads and stores - Advanced SIMD Load/Store single structures + bool ST1_sngl_1(bool Q, bool S, Imm<2> size, Reg Rn, Vec Vt); + bool ST1_sngl_2(bool Q, Reg Rm, bool S, Imm<2> size, Reg Rn, Vec Vt); + bool ST3_sngl_1(bool Q, bool S, Imm<2> size, Reg Rn, Vec Vt); + bool ST3_sngl_2(bool Q, Reg Rm, bool S, Imm<2> size, Reg Rn, Vec Vt); + bool ST2_sngl_1(bool Q, bool S, Imm<2> size, Reg Rn, Vec Vt); + bool ST2_sngl_2(bool Q, Reg Rm, bool S, Imm<2> size, Reg Rn, Vec Vt); + bool ST4_sngl_1(bool Q, bool S, Imm<2> size, Reg Rn, Vec Vt); + bool ST4_sngl_2(bool Q, Reg Rm, bool S, Imm<2> size, Reg Rn, Vec Vt); + bool LD1_sngl_1(bool Q, bool S, Imm<2> size, Reg Rn, Vec Vt); + bool LD1_sngl_2(bool Q, Reg Rm, bool S, Imm<2> size, Reg Rn, Vec Vt); + bool LD3_sngl_1(bool Q, bool S, Imm<2> size, Reg Rn, Vec Vt); + bool LD3_sngl_2(bool Q, Reg Rm, bool S, Imm<2> size, Reg Rn, Vec Vt); + bool LD1R_1(bool Q, Imm<2> size, Reg Rn, Vec Vt); + bool LD1R_2(bool Q, Reg Rm, Imm<2> size, Reg Rn, Vec Vt); + bool LD3R_1(bool Q, Imm<2> size, Reg Rn, Vec Vt); + bool LD3R_2(bool Q, Reg Rm, Imm<2> size, Reg Rn, Vec Vt); + bool LD2_sngl_1(bool Q, bool S, Imm<2> size, Reg Rn, Vec Vt); + bool LD2_sngl_2(bool Q, Reg Rm, bool S, Imm<2> size, Reg Rn, Vec Vt); + bool LD4_sngl_1(bool Q, bool S, Imm<2> size, Reg Rn, Vec Vt); + bool LD4_sngl_2(bool Q, Reg Rm, bool S, Imm<2> size, Reg Rn, Vec Vt); + bool LD2R_1(bool Q, Imm<2> size, Reg Rn, Vec Vt); + bool LD2R_2(bool Q, Reg Rm, Imm<2> size, Reg Rn, Vec Vt); + bool LD4R_1(bool Q, Imm<2> size, Reg Rn, Vec Vt); + bool LD4R_2(bool Q, Reg Rm, Imm<2> size, Reg Rn, Vec Vt); + + // Loads and stores - Load/Store Exclusive + bool STXRB(Reg Rs, Reg Rn, Reg Rt); + bool STLXRB(Reg Rs, Reg Rn, Reg Rt); + bool CASP(bool sz, bool L, Reg Rs, bool o0, Reg Rn, Reg Rt); + bool LDXRB(Reg Rn, Reg Rt); + bool LDAXRB(Reg Rn, Reg Rt); + bool STLLRB(Reg Rn, Reg Rt); + bool STLRB(Reg Rn, Reg Rt); + bool CASB(bool L, Reg Rs, bool o0, Reg Rn, Reg Rt); + bool LDLARB(Reg Rn, Reg Rt); + bool LDARB(Reg Rn, Reg Rt); + bool STXRH(Reg Rs, Reg Rn, Reg Rt); + bool STLXRH(Reg Rs, Reg Rn, Reg Rt); + bool LDXRH(Reg Rn, Reg Rt); + bool LDAXRH(Reg Rn, Reg Rt); + bool STLLRH(Reg Rn, Reg Rt); + bool STLRH(Reg Rn, Reg Rt); + bool CASH(bool L, Reg Rs, bool o0, Reg Rn, Reg Rt); + bool LDLARH(Reg Rn, Reg Rt); + bool LDARH(Reg Rn, Reg Rt); + bool STXR(Reg Rs, Reg Rn, Reg Rt); + bool STLXR(Reg Rs, Reg Rn, Reg Rt); + bool STXP(bool sz, Reg Rs, Reg Rt2, Reg Rn, Reg Rt); + bool STLXP(bool sz, Reg Rs, Reg Rt2, Reg Rn, Reg Rt); + bool LDXR(Reg Rn, Reg Rt); + bool LDAXR(Reg Rn, Reg Rt); + bool LDXP(bool sz, Reg Rt2, Reg Rn, Reg Rt); + bool LDAXP(bool sz, Reg Rt2, Reg Rn, Reg Rt); + bool STLLR(Reg Rn, Reg Rt); + bool STLR(Reg Rn, Reg Rt); + bool CAS(bool L, Reg Rs, bool o0, Reg Rn, Reg Rt); + bool LDLAR(Reg Rn, Reg Rt); + bool LDAR(Reg Rn, Reg Rt); + + // Loads and stores - Load register (literal) + bool LDR_lit_gen(Imm<19> imm19, Reg Rt); + bool LDR_lit_fpsimd(Imm<2> opc, Imm<19> imm19, Vec Vt); + bool LDRSW_lit(Imm<19> imm19, Reg Rt); + bool PRFM_lit(Imm<19> imm19, Reg Rt); + + // Loads and stores - Load/Store no-allocate pair + bool STNP_gen(Imm<7> imm7, Reg Rt2, Reg Rn, Reg Rt); + bool LDNP_gen(Imm<7> imm7, Reg Rt2, Reg Rn, Reg Rt); + bool STNP_fpsimd(Imm<2> opc, Imm<7> imm7, Vec Vt2, Reg Rn, Vec Vt); + bool LDNP_fpsimd(Imm<2> opc, Imm<7> imm7, Vec Vt2, Reg Rn, Vec Vt); + + // Loads and stores - Load/Store register pair + bool STP_gen_1(Imm<7> imm7, Reg Rt2, Reg Rn, Reg Rt); + bool STP_gen_2(Imm<7> imm7, Reg Rt2, Reg Rn, Reg Rt); + bool STP_gen_3(Imm<7> imm7, Reg Rt2, Reg Rn, Reg Rt); + bool LDP_gen_1(Imm<7> imm7, Reg Rt2, Reg Rn, Reg Rt); + bool LDP_gen_2(Imm<7> imm7, Reg Rt2, Reg Rn, Reg Rt); + bool LDP_gen_3(Imm<7> imm7, Reg Rt2, Reg Rn, Reg Rt); + bool STP_fpsimd_1(Imm<2> opc, Imm<7> imm7, Vec Vt2, Reg Rn, Vec Vt); + bool STP_fpsimd_2(Imm<2> opc, Imm<7> imm7, Vec Vt2, Reg Rn, Vec Vt); + bool STP_fpsimd_3(Imm<2> opc, Imm<7> imm7, Vec Vt2, Reg Rn, Vec Vt); + bool LDP_fpsimd_1(Imm<2> opc, Imm<7> imm7, Vec Vt2, Reg Rn, Vec Vt); + bool LDP_fpsimd_2(Imm<2> opc, Imm<7> imm7, Vec Vt2, Reg Rn, Vec Vt); + bool LDP_fpsimd_3(Imm<2> opc, Imm<7> imm7, Vec Vt2, Reg Rn, Vec Vt); + bool LDPSW_1(Imm<7> imm7, Reg Rt2, Reg Rn, Reg Rt); + bool LDPSW_2(Imm<7> imm7, Reg Rt2, Reg Rn, Reg Rt); + bool LDPSW_3(Imm<7> imm7, Reg Rt2, Reg Rn, Reg Rt); + + // Loads and stores - Load/Store register (unscaled immediate) + bool STURB(Imm<9> imm9, Reg Rn, Reg Rt); + bool LDURB(Imm<9> imm9, Reg Rn, Reg Rt); + bool LDURSB(Imm<9> imm9, Reg Rn, Reg Rt); + bool STUR_fpsimd(Imm<2> size, Imm<9> imm9, Reg Rn, Vec Vt); + bool LDUR_fpsimd(Imm<2> size, Imm<9> imm9, Reg Rn, Vec Vt); + bool STURH(Imm<9> imm9, Reg Rn, Reg Rt); + bool LDURH(Imm<9> imm9, Reg Rn, Reg Rt); + bool LDURSH(Imm<9> imm9, Reg Rn, Reg Rt); + bool STUR_gen(Imm<9> imm9, Reg Rn, Reg Rt); + bool LDUR_gen(Imm<9> imm9, Reg Rn, Reg Rt); + bool LDURSW(Imm<9> imm9, Reg Rn, Reg Rt); + bool PRFUM(Imm<9> imm9, Reg Rn, Reg Rt); + bool PRFM_imm(Imm<12> imm12, Reg Rn, Reg Rt); + + // Loads and stores - Load/Store register (immediate pre/post-indexed) + bool STRB_imm_1(Imm<9> imm9, Reg Rn, Reg Rt); + bool STRB_imm_2(Imm<9> imm9, Reg Rn, Reg Rt); + bool STRB_imm_3(Imm<12> imm12, Reg Rn, Reg Rt); + bool LDRB_imm_1(Imm<9> imm9, Reg Rn, Reg Rt); + bool LDRB_imm_2(Imm<9> imm9, Reg Rn, Reg Rt); + bool LDRB_imm_3(Imm<12> imm12, Reg Rn, Reg Rt); + bool LDRSB_imm_1(Imm<9> imm9, Reg Rn, Reg Rt); + bool LDRSB_imm_2(Imm<9> imm9, Reg Rn, Reg Rt); + bool LDRSB_imm_3(Imm<12> imm12, Reg Rn, Reg Rt); + bool STR_imm_fpsimd_1(Imm<2> size, Imm<9> imm9, Reg Rn, Vec Vt); + bool STR_imm_fpsimd_2(Imm<2> size, Imm<9> imm9, Reg Rn, Vec Vt); + bool STR_imm_fpsimd_3(Imm<2> size, Imm<12> imm12, Reg Rn, Vec Vt); + bool LDR_imm_fpsimd_1(Imm<2> size, Imm<9> imm9, Reg Rn, Vec Vt); + bool LDR_imm_fpsimd_2(Imm<2> size, Imm<9> imm9, Reg Rn, Vec Vt); + bool LDR_imm_fpsimd_3(Imm<2> size, Imm<12> imm12, Reg Rn, Vec Vt); + bool STRH_imm_1(Imm<9> imm9, Reg Rn, Reg Rt); + bool STRH_imm_2(Imm<9> imm9, Reg Rn, Reg Rt); + bool STRH_imm_3(Imm<12> imm12, Reg Rn, Reg Rt); + bool LDRH_imm_1(Imm<9> imm9, Reg Rn, Reg Rt); + bool LDRH_imm_2(Imm<9> imm9, Reg Rn, Reg Rt); + bool LDRH_imm_3(Imm<12> imm12, Reg Rn, Reg Rt); + bool LDRSH_imm_1(Imm<9> imm9, Reg Rn, Reg Rt); + bool LDRSH_imm_2(Imm<9> imm9, Reg Rn, Reg Rt); + bool LDRSH_imm_3(Imm<12> imm12, Reg Rn, Reg Rt); + bool STR_imm_gen_1(Imm<9> imm9, Reg Rn, Reg Rt); + bool STR_imm_gen_2(Imm<9> imm9, Reg Rn, Reg Rt); + bool STR_imm_gen_3(Imm<12> imm12, Reg Rn, Reg Rt); + bool LDR_imm_gen_1(Imm<9> imm9, Reg Rn, Reg Rt); + bool LDR_imm_gen_2(Imm<9> imm9, Reg Rn, Reg Rt); + bool LDR_imm_gen_3(Imm<12> imm12, Reg Rn, Reg Rt); + bool LDRSW_imm_1(Imm<9> imm9, Reg Rn, Reg Rt); + bool LDRSW_imm_2(Imm<9> imm9, Reg Rn, Reg Rt); + bool LDRSW_imm_3(Imm<12> imm12, Reg Rn, Reg Rt); + + // Loads and stores - Load/Store register (unprivileged) + bool STTRB(Imm<9> imm9, Reg Rn, Reg Rt); + bool LDTRB(Imm<9> imm9, Reg Rn, Reg Rt); + bool LDTRSB(Imm<9> imm9, Reg Rn, Reg Rt); + bool STTRH(Imm<9> imm9, Reg Rn, Reg Rt); + bool LDTRH(Imm<9> imm9, Reg Rn, Reg Rt); + bool LDTRSH(Imm<9> imm9, Reg Rn, Reg Rt); + bool STTR(Imm<9> imm9, Reg Rn, Reg Rt); + bool LDTR(Imm<9> imm9, Reg Rn, Reg Rt); + bool LDTRSW(Imm<9> imm9, Reg Rn, Reg Rt); + + // Loads and stores - Atomic memory options + bool LDADDB(bool A, bool R, Reg Rs, Reg Rn, Reg Rt); + bool LDCLRB(bool A, bool R, Reg Rs, Reg Rn, Reg Rt); + bool LDEORB(bool A, bool R, Reg Rs, Reg Rn, Reg Rt); + bool LDSETB(bool A, bool R, Reg Rs, Reg Rn, Reg Rt); + bool LDSMAXB(bool A, bool R, Reg Rs, Reg Rn, Reg Rt); + bool LDSMINB(bool A, bool R, Reg Rs, Reg Rn, Reg Rt); + bool LDUMAXB(bool A, bool R, Reg Rs, Reg Rn, Reg Rt); + bool LDUMINB(bool A, bool R, Reg Rs, Reg Rn, Reg Rt); + bool SWPB(bool A, bool R, Reg Rs, Reg Rn, Reg Rt); + bool LDAPRB(Reg Rn, Reg Rt); + bool LDADDH(bool A, bool R, Reg Rs, Reg Rn, Reg Rt); + bool LDCLRH(bool A, bool R, Reg Rs, Reg Rn, Reg Rt); + bool LDEORH(bool A, bool R, Reg Rs, Reg Rn, Reg Rt); + bool LDSETH(bool A, bool R, Reg Rs, Reg Rn, Reg Rt); + bool LDSMAXH(bool A, bool R, Reg Rs, Reg Rn, Reg Rt); + bool LDSMINH(bool A, bool R, Reg Rs, Reg Rn, Reg Rt); + bool LDUMAXH(bool A, bool R, Reg Rs, Reg Rn, Reg Rt); + bool LDUMINH(bool A, bool R, Reg Rs, Reg Rn, Reg Rt); + bool SWPH(bool A, bool R, Reg Rs, Reg Rn, Reg Rt); + bool LDAPRH(Reg Rn, Reg Rt); + bool LDADD(bool A, bool R, Reg Rs, Reg Rn, Reg Rt); + bool LDCLR(bool A, bool R, Reg Rs, Reg Rn, Reg Rt); + bool LDEOR(bool A, bool R, Reg Rs, Reg Rn, Reg Rt); + bool LDSET(bool A, bool R, Reg Rs, Reg Rn, Reg Rt); + bool LDSMAX(bool A, bool R, Reg Rs, Reg Rn, Reg Rt); + bool LDSMIN(bool A, bool R, Reg Rs, Reg Rn, Reg Rt); + bool LDUMAX(bool A, bool R, Reg Rs, Reg Rn, Reg Rt); + bool LDUMIN(bool A, bool R, Reg Rs, Reg Rn, Reg Rt); + bool SWP(bool A, bool R, Reg Rs, Reg Rn, Reg Rt); + bool LDAPR(Reg Rn, Reg Rt); + + // Loads and stores - Load/Store register (register offset) + bool STRB_reg(Reg Rm, Imm<3> option, bool S, Reg Rn, Reg Rt); + bool LDRB_reg(Reg Rm, Imm<3> option, bool S, Reg Rn, Reg Rt); + bool LDRSB_reg(Reg Rm, Imm<3> option, bool S, Reg Rn, Reg Rt); + bool STR_reg_fpsimd(Imm<2> size, Reg Rm, Imm<3> option, bool S, Reg Rn, Vec Vt); + bool LDR_reg_fpsimd(Imm<2> size, Reg Rm, Imm<3> option, bool S, Reg Rn, Vec Vt); + bool STRH_reg(Reg Rm, Imm<3> option, bool S, Reg Rn, Reg Rt); + bool LDRH_reg(Reg Rm, Imm<3> option, bool S, Reg Rn, Reg Rt); + bool LDRSH_reg(Reg Rm, Imm<3> option, bool S, Reg Rn, Reg Rt); + bool STR_reg_gen(Reg Rm, Imm<3> option, bool S, Reg Rn, Reg Rt); + bool LDR_reg_gen(Reg Rm, Imm<3> option, bool S, Reg Rn, Reg Rt); + bool LDRSW_reg(Reg Rm, Imm<3> option, bool S, Reg Rn, Reg Rt); + bool PRFM_reg(Reg Rm, Imm<3> option, bool S, Reg Rn, Reg Rt); + + // Loads and stores - Load/Store register (pointer authentication) + bool LDRA(bool M, bool S, Imm<9> imm9, bool W, Reg Rn, Reg Rt); + + // Data Processing - Register - 2 source + bool UDIV(bool sf, Reg Rm, Reg Rn, Reg Rd); + bool SDIV(bool sf, Reg Rm, Reg Rn, Reg Rd); + bool LSLV(bool sf, Reg Rm, Reg Rn, Reg Rd); + bool LSRV(bool sf, Reg Rm, Reg Rn, Reg Rd); + bool ASRV(bool sf, Reg Rm, Reg Rn, Reg Rd); + bool RORV(bool sf, Reg Rm, Reg Rn, Reg Rd); + bool CRC32(bool sf, Reg Rm, Imm<2> sz, Reg Rn, Reg Rd); + bool CRC32C(bool sf, Reg Rm, Imm<2> sz, Reg Rn, Reg Rd); + bool PACGA(Reg Rm, Reg Rn, Reg Rd); + + // Data Processing - Register - 1 source + bool RBIT_int(bool sf, Reg Rn, Reg Rd); + bool REV16_int(bool sf, Reg Rn, Reg Rd); + bool REV(bool sf, Reg Rn, Reg Rd); + bool CLZ_int(bool sf, Reg Rn, Reg Rd); + bool CLS_int(bool sf, Reg Rn, Reg Rd); + bool REV32_int(Reg Rn, Reg Rd); + bool PACDA(bool Z, Reg Rn, Reg Rd); + bool PACDB(bool Z, Reg Rn, Reg Rd); + bool AUTDA(bool Z, Reg Rn, Reg Rd); + bool AUTDB(bool Z, Reg Rn, Reg Rd); + + // Data Processing - Register - Logical (shifted register) + bool AND_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd); + bool BIC_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd); + bool ORR_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd); + bool ORN_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd); + bool EOR_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd); + bool EON(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd); + bool ANDS_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd); + bool BICS(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd); + + // Data Processing - Register - Add/Sub (shifted register) + bool ADD_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd); + bool ADDS_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd); + bool SUB_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd); + bool SUBS_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd); + + // Data Processing - Register - Add/Sub (shifted register) + bool ADD_ext(bool sf, Reg Rm, Imm<3> option, Imm<3> imm3, Reg Rn, Reg Rd); + bool ADDS_ext(bool sf, Reg Rm, Imm<3> option, Imm<3> imm3, Reg Rn, Reg Rd); + bool SUB_ext(bool sf, Reg Rm, Imm<3> option, Imm<3> imm3, Reg Rn, Reg Rd); + bool SUBS_ext(bool sf, Reg Rm, Imm<3> option, Imm<3> imm3, Reg Rn, Reg Rd); + + // Data Processing - Register - Add/Sub (with carry) + bool ADC(bool sf, Reg Rm, Reg Rn, Reg Rd); + bool ADCS(bool sf, Reg Rm, Reg Rn, Reg Rd); + bool SBC(bool sf, Reg Rm, Reg Rn, Reg Rd); + bool SBCS(bool sf, Reg Rm, Reg Rn, Reg Rd); + + // Data Processing - Register - Conditional compare + bool CCMN_reg(bool sf, Reg Rm, Cond cond, Reg Rn, Imm<4> nzcv); + bool CCMP_reg(bool sf, Reg Rm, Cond cond, Reg Rn, Imm<4> nzcv); + bool CCMN_imm(bool sf, Imm<5> imm5, Cond cond, Reg Rn, Imm<4> nzcv); + bool CCMP_imm(bool sf, Imm<5> imm5, Cond cond, Reg Rn, Imm<4> nzcv); + + // Data Processing - Register - Conditional select + bool CSEL(bool sf, Reg Rm, Cond cond, Reg Rn, Reg Rd); + bool CSINC(bool sf, Reg Rm, Cond cond, Reg Rn, Reg Rd); + bool CSINV(bool sf, Reg Rm, Cond cond, Reg Rn, Reg Rd); + bool CSNEG(bool sf, Reg Rm, Cond cond, Reg Rn, Reg Rd); + + // Data Processing - Register - 3 source + bool MADD(bool sf, Reg Rm, Reg Ra, Reg Rn, Reg Rd); + bool MSUB(bool sf, Reg Rm, Reg Ra, Reg Rn, Reg Rd); + bool SMADDL(Reg Rm, Reg Ra, Reg Rn, Reg Rd); + bool SMSUBL(Reg Rm, Reg Ra, Reg Rn, Reg Rd); + bool SMULH(Reg Rm, Reg Rn, Reg Rd); + bool UMADDL(Reg Rm, Reg Ra, Reg Rn, Reg Rd); + bool UMSUBL(Reg Rm, Reg Ra, Reg Rn, Reg Rd); + bool UMULH(Reg Rm, Reg Rn, Reg Rd); + + // Data Processing - FP and SIMD - AES + bool AESE(Vec Vn, Vec Vd); + bool AESD(Vec Vn, Vec Vd); + bool AESMC(Vec Vn, Vec Vd); + bool AESIMC(Vec Vn, Vec Vd); + + // Data Processing - FP and SIMD - SHA + bool SHA1C(Vec Vm, Vec Vn, Vec Vd); + bool SHA1P(Vec Vm, Vec Vn, Vec Vd); + bool SHA1M(Vec Vm, Vec Vn, Vec Vd); + bool SHA1SU0(Vec Vm, Vec Vn, Vec Vd); + bool SHA256H(Vec Vm, Vec Vn, Vec Vd); + bool SHA256H2(Vec Vm, Vec Vn, Vec Vd); + bool SHA256SU1(Vec Vm, Vec Vn, Vec Vd); + bool SHA1H(Vec Vn, Vec Vd); + bool SHA1SU1(Vec Vn, Vec Vd); + bool SHA256SU0(Vec Vn, Vec Vd); + + // Data Processing - FP and SIMD - Scalar copy + bool DUP_elt_1(Imm<5> imm5, Vec Vn, Vec Vd); + bool DUP_elt_2(bool Q, Imm<5> imm5, Vec Vn, Vec Vd); + + // Data Processing - FP and SIMD - Scalar three + bool FMULX_vec_1(Vec Vm, Vec Vn, Vec Vd); + bool FMULX_vec_2(bool sz, Vec Vm, Vec Vn, Vec Vd); + bool FMULX_vec_3(bool Q, Vec Vm, Vec Vn, Vec Vd); + bool FMULX_vec_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd); + bool FCMEQ_reg_1(Vec Vm, Vec Vn, Vec Vd); + bool FCMEQ_reg_2(bool sz, Vec Vm, Vec Vn, Vec Vd); + bool FCMEQ_reg_3(bool Q, Vec Vm, Vec Vn, Vec Vd); + bool FCMEQ_reg_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd); + bool FRECPS_1(Vec Vm, Vec Vn, Vec Vd); + bool FRECPS_2(bool sz, Vec Vm, Vec Vn, Vec Vd); + bool FRECPS_3(bool Q, Vec Vm, Vec Vn, Vec Vd); + bool FRECPS_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd); + bool FRSQRTS_1(Vec Vm, Vec Vn, Vec Vd); + bool FRSQRTS_2(bool sz, Vec Vm, Vec Vn, Vec Vd); + bool FRSQRTS_3(bool Q, Vec Vm, Vec Vn, Vec Vd); + bool FRSQRTS_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd); + bool FCMGE_reg_1(Vec Vm, Vec Vn, Vec Vd); + bool FCMGE_reg_2(bool sz, Vec Vm, Vec Vn, Vec Vd); + bool FCMGE_reg_3(bool Q, Vec Vm, Vec Vn, Vec Vd); + bool FCMGE_reg_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd); + bool FACGE_1(Vec Vm, Vec Vn, Vec Vd); + bool FACGE_2(bool sz, Vec Vm, Vec Vn, Vec Vd); + bool FACGE_3(bool Q, Vec Vm, Vec Vn, Vec Vd); + bool FACGE_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd); + bool FABD_1(Vec Vm, Vec Vn, Vec Vd); + bool FABD_2(bool sz, Vec Vm, Vec Vn, Vec Vd); + bool FABD_3(bool Q, Vec Vm, Vec Vn, Vec Vd); + bool FABD_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd); + bool FCMGT_reg_1(Vec Vm, Vec Vn, Vec Vd); + bool FCMGT_reg_2(bool sz, Vec Vm, Vec Vn, Vec Vd); + bool FCMGT_reg_3(bool Q, Vec Vm, Vec Vn, Vec Vd); + bool FCMGT_reg_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd); + bool FACGT_1(Vec Vm, Vec Vn, Vec Vd); + bool FACGT_2(bool sz, Vec Vm, Vec Vn, Vec Vd); + bool FACGT_3(bool Q, Vec Vm, Vec Vn, Vec Vd); + bool FACGT_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd); + + // Data Processing - FP and SIMD - Two register misc + bool FCVTNS_1(Vec Vn, Vec Vd); + bool FCVTNS_2(bool sz, Vec Vn, Vec Vd); + bool FCVTNS_3(bool Q, Vec Vn, Vec Vd); + bool FCVTNS_4(bool Q, bool sz, Vec Vn, Vec Vd); + bool FCVTMS_1(Vec Vn, Vec Vd); + bool FCVTMS_2(bool sz, Vec Vn, Vec Vd); + bool FCVTMS_3(bool Q, Vec Vn, Vec Vd); + bool FCVTMS_4(bool Q, bool sz, Vec Vn, Vec Vd); + bool FCVTAS_1(Vec Vn, Vec Vd); + bool FCVTAS_2(bool sz, Vec Vn, Vec Vd); + bool FCVTAS_3(bool Q, Vec Vn, Vec Vd); + bool FCVTAS_4(bool Q, bool sz, Vec Vn, Vec Vd); + bool SCVTF_int_1(Vec Vn, Vec Vd); + bool SCVTF_int_2(bool sz, Vec Vn, Vec Vd); + bool SCVTF_int_3(bool Q, Vec Vn, Vec Vd); + bool SCVTF_int_4(bool Q, bool sz, Vec Vn, Vec Vd); + bool FCMGT_zero_1(Vec Vn, Vec Vd); + bool FCMGT_zero_2(bool sz, Vec Vn, Vec Vd); + bool FCMGT_zero_3(bool Q, Vec Vn, Vec Vd); + bool FCMGT_zero_4(bool Q, bool sz, Vec Vn, Vec Vd); + bool FCMEQ_zero_1(Vec Vn, Vec Vd); + bool FCMEQ_zero_2(bool sz, Vec Vn, Vec Vd); + bool FCMEQ_zero_3(bool Q, Vec Vn, Vec Vd); + bool FCMEQ_zero_4(bool Q, bool sz, Vec Vn, Vec Vd); + bool FCMLT_1(Vec Vn, Vec Vd); + bool FCMLT_2(bool sz, Vec Vn, Vec Vd); + bool FCMLT_3(bool Q, Vec Vn, Vec Vd); + bool FCMLT_4(bool Q, bool sz, Vec Vn, Vec Vd); + bool FCVTPS_1(Vec Vn, Vec Vd); + bool FCVTPS_2(bool sz, Vec Vn, Vec Vd); + bool FCVTPS_3(bool Q, Vec Vn, Vec Vd); + bool FCVTPS_4(bool Q, bool sz, Vec Vn, Vec Vd); + bool FCVTZS_int_1(Vec Vn, Vec Vd); + bool FCVTZS_int_2(bool sz, Vec Vn, Vec Vd); + bool FCVTZS_int_3(bool Q, Vec Vn, Vec Vd); + bool FCVTZS_int_4(bool Q, bool sz, Vec Vn, Vec Vd); + bool FRECPE_1(Vec Vn, Vec Vd); + bool FRECPE_2(bool sz, Vec Vn, Vec Vd); + bool FRECPE_3(bool Q, Vec Vn, Vec Vd); + bool FRECPE_4(bool Q, bool sz, Vec Vn, Vec Vd); + bool FRECPX_1(Vec Vn, Vec Vd); + bool FRECPX_2(bool sz, Vec Vn, Vec Vd); + bool FCVTNU_1(Vec Vn, Vec Vd); + bool FCVTNU_2(bool sz, Vec Vn, Vec Vd); + bool FCVTNU_3(bool Q, Vec Vn, Vec Vd); + bool FCVTNU_4(bool Q, bool sz, Vec Vn, Vec Vd); + bool FCVTMU_1(Vec Vn, Vec Vd); + bool FCVTMU_2(bool sz, Vec Vn, Vec Vd); + bool FCVTMU_3(bool Q, Vec Vn, Vec Vd); + bool FCVTMU_4(bool Q, bool sz, Vec Vn, Vec Vd); + bool FCVTAU_1(Vec Vn, Vec Vd); + bool FCVTAU_2(bool sz, Vec Vn, Vec Vd); + bool FCVTAU_3(bool Q, Vec Vn, Vec Vd); + bool FCVTAU_4(bool Q, bool sz, Vec Vn, Vec Vd); + bool UCVTF_int_1(Vec Vn, Vec Vd); + bool UCVTF_int_2(bool sz, Vec Vn, Vec Vd); + bool UCVTF_int_3(bool Q, Vec Vn, Vec Vd); + bool UCVTF_int_4(bool Q, bool sz, Vec Vn, Vec Vd); + bool FCMGE_zero_1(Vec Vn, Vec Vd); + bool FCMGE_zero_2(bool sz, Vec Vn, Vec Vd); + bool FCMGE_zero_3(bool Q, Vec Vn, Vec Vd); + bool FCMGE_zero_4(bool Q, bool sz, Vec Vn, Vec Vd); + bool FCMLE_1(Vec Vn, Vec Vd); + bool FCMLE_2(bool sz, Vec Vn, Vec Vd); + bool FCMLE_3(bool Q, Vec Vn, Vec Vd); + bool FCMLE_4(bool Q, bool sz, Vec Vn, Vec Vd); + bool FCVTPU_1(Vec Vn, Vec Vd); + bool FCVTPU_2(bool sz, Vec Vn, Vec Vd); + bool FCVTPU_3(bool Q, Vec Vn, Vec Vd); + bool FCVTPU_4(bool Q, bool sz, Vec Vn, Vec Vd); + bool FCVTZU_int_1(Vec Vn, Vec Vd); + bool FCVTZU_int_2(bool sz, Vec Vn, Vec Vd); + bool FCVTZU_int_3(bool Q, Vec Vn, Vec Vd); + bool FCVTZU_int_4(bool Q, bool sz, Vec Vn, Vec Vd); + bool FRSQRTE_1(Vec Vn, Vec Vd); + bool FRSQRTE_2(bool sz, Vec Vn, Vec Vd); + bool FRSQRTE_3(bool Q, Vec Vn, Vec Vd); + bool FRSQRTE_4(bool Q, bool sz, Vec Vn, Vec Vd); + + // Data Processing - FP and SIMD - Scalar three same extra + bool SQRDMLAH_vec_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool SQRDMLAH_vec_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool SQRDMLSH_vec_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool SQRDMLSH_vec_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + + // Data Processing - FP and SIMD - Scalar two-register misc + bool SUQADD_1(Imm<2> size, Vec Vn, Vec Vd); + bool SUQADD_2(bool Q, Imm<2> size, Vec Vn, Vec Vd); + bool SQABS_1(Imm<2> size, Vec Vn, Vec Vd); + bool SQABS_2(bool Q, Imm<2> size, Vec Vn, Vec Vd); + bool CMGT_zero_1(Imm<2> size, Vec Vn, Vec Vd); + bool CMGT_zero_2(bool Q, Imm<2> size, Vec Vn, Vec Vd); + bool CMEQ_zero_1(Imm<2> size, Vec Vn, Vec Vd); + bool CMEQ_zero_2(bool Q, Imm<2> size, Vec Vn, Vec Vd); + bool CMLT_1(Imm<2> size, Vec Vn, Vec Vd); + bool CMLT_2(bool Q, Imm<2> size, Vec Vn, Vec Vd); + bool ABS_1(Imm<2> size, Vec Vn, Vec Vd); + bool ABS_2(bool Q, Imm<2> size, Vec Vn, Vec Vd); + bool SQXTN_1(Imm<2> size, Vec Vn, Reg Rd); + bool SQXTN_2(bool Q, Imm<2> size, Vec Vn, Reg Rd); + bool USQADD_1(Imm<2> size, Vec Vn, Vec Vd); + bool USQADD_2(bool Q, Imm<2> size, Vec Vn, Vec Vd); + bool SQNEG_1(Imm<2> size, Vec Vn, Vec Vd); + bool SQNEG_2(bool Q, Imm<2> size, Vec Vn, Vec Vd); + bool CMGE_zero_1(Imm<2> size, Vec Vn, Vec Vd); + bool CMGE_zero_2(bool Q, Imm<2> size, Vec Vn, Vec Vd); + bool CMLE_1(Imm<2> size, Vec Vn, Vec Vd); + bool CMLE_2(bool Q, Imm<2> size, Vec Vn, Vec Vd); + bool NEG_1(Imm<2> size, Vec Vn, Vec Vd); + bool NEG_2(bool Q, Imm<2> size, Vec Vn, Vec Vd); + bool SQXTUN_1(Imm<2> size, Vec Vn, Reg Rd); + bool SQXTUN_2(bool Q, Imm<2> size, Vec Vn, Reg Rd); + bool UQXTN_1(Imm<2> size, Vec Vn, Reg Rd); + bool UQXTN_2(bool Q, Imm<2> size, Vec Vn, Reg Rd); + bool FCVTXN_1(bool sz, Vec Vn, Reg Rd); + bool FCVTXN_2(bool Q, bool sz, Vec Vn, Reg Rd); + + // Data Processing - FP and SIMD - SIMD Scalar pairwise + bool ADDP_pair(Imm<2> size, Vec Vn, Vec Vd); + bool FMAXNMP_pair_1(Vec Vn, Vec Vd); + bool FMAXNMP_pair_2(bool sz, Vec Vn, Vec Vd); + bool FADDP_pair_1(Vec Vn, Vec Vd); + bool FADDP_pair_2(bool sz, Vec Vn, Vec Vd); + bool FMAXP_pair_1(Vec Vn, Vec Vd); + bool FMAXP_pair_2(bool sz, Vec Vn, Vec Vd); + bool FMINNMP_pair_1(Vec Vn, Vec Vd); + bool FMINNMP_pair_2(bool sz, Vec Vn, Vec Vd); + bool FMINP_pair_1(Vec Vn, Vec Vd); + bool FMINP_pair_2(bool sz, Vec Vn, Vec Vd); + + // Data Processing - FP and SIMD - SIMD Scalar three different + bool SQDMLAL_vec_1(Imm<2> size, Reg Rm, Reg Rn, Vec Vd); + bool SQDMLAL_vec_2(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd); + bool SQDMLSL_vec_1(Imm<2> size, Reg Rm, Reg Rn, Vec Vd); + bool SQDMLSL_vec_2(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd); + bool SQDMULL_vec_1(Imm<2> size, Reg Rm, Reg Rn, Vec Vd); + bool SQDMULL_vec_2(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd); + + // Data Processing - FP and SIMD - SIMD Scalar three same + bool SQADD_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool SQADD_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool SQSUB_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool SQSUB_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool CMGT_reg_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool CMGT_reg_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool CMGE_reg_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool CMGE_reg_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool SSHL_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool SSHL_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool SQSHL_reg_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool SQSHL_reg_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool SRSHL_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool SRSHL_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool SQRSHL_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool SQRSHL_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool ADD_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool ADD_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool CMTST_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool CMTST_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool SQDMULH_vec_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool SQDMULH_vec_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool UQADD_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool UQADD_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool UQSUB_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool UQSUB_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool CMHI_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool CMHI_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool CMHS_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool CMHS_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool USHL_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool USHL_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool UQSHL_reg_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool UQSHL_reg_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool URSHL_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool URSHL_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool UQRSHL_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool UQRSHL_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool SUB_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool SUB_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool CMEQ_reg_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool CMEQ_reg_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool SQRDMULH_vec_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool SQRDMULH_vec_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + + // Data Processing - FP and SIMD - SIMD Scalar shift by immediate + bool SSHR_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd); + bool SSHR_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd); + bool SSRA_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd); + bool SSRA_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd); + bool SRSHR_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd); + bool SRSHR_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd); + bool SRSRA_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd); + bool SRSRA_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd); + bool SHL_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd); + bool SHL_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd); + bool SQSHL_imm_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd); + bool SQSHL_imm_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd); + bool SQSHRN_1(Imm<4> immh, Imm<3> immb, Vec Vn, Reg Rd); + bool SQSHRN_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Reg Rd); + bool SQRSHRN_1(Imm<4> immh, Imm<3> immb, Vec Vn, Reg Rd); + bool SQRSHRN_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Reg Rd); + bool SCVTF_fix_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd); + bool SCVTF_fix_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd); + bool FCVTZS_fix_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd); + bool FCVTZS_fix_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd); + bool USHR_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd); + bool USHR_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd); + bool USRA_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd); + bool USRA_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd); + bool URSHR_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd); + bool URSHR_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd); + bool URSRA_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd); + bool URSRA_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd); + bool SRI_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd); + bool SRI_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd); + bool SLI_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd); + bool SLI_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd); + bool SQSHLU_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd); + bool SQSHLU_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd); + bool UQSHL_imm_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd); + bool UQSHL_imm_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd); + bool SQSHRUN_1(Imm<4> immh, Imm<3> immb, Vec Vn, Reg Rd); + bool SQSHRUN_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Reg Rd); + bool SQRSHRUN_1(Imm<4> immh, Imm<3> immb, Vec Vn, Reg Rd); + bool SQRSHRUN_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Reg Rd); + bool UQSHRN_1(Imm<4> immh, Imm<3> immb, Vec Vn, Reg Rd); + bool UQSHRN_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Reg Rd); + bool UQRSHRN_1(Imm<4> immh, Imm<3> immb, Vec Vn, Reg Rd); + bool UQRSHRN_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Reg Rd); + bool UCVTF_fix_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd); + bool UCVTF_fix_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd); + bool FCVTZU_fix_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd); + bool FCVTZU_fix_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd); + + // Data Processing - FP and SIMD - SIMD Scalar x indexed element + bool SQDMLAL_elt_1(Imm<2> size, bool L, bool M, Vec Vm, bool H, Reg Rn, Vec Vd); + bool SQDMLAL_elt_2(bool Q, Imm<2> size, bool L, bool M, Vec Vm, bool H, Reg Rn, Vec Vd); + bool SQDMLSL_elt_1(Imm<2> size, bool L, bool M, Vec Vm, bool H, Reg Rn, Vec Vd); + bool SQDMLSL_elt_2(bool Q, Imm<2> size, bool L, bool M, Vec Vm, bool H, Reg Rn, Vec Vd); + bool SQDMULL_elt_1(Imm<2> size, bool L, bool M, Vec Vm, bool H, Reg Rn, Vec Vd); + bool SQDMULL_elt_2(bool Q, Imm<2> size, bool L, bool M, Vec Vm, bool H, Reg Rn, Vec Vd); + bool SQDMULH_elt_1(Imm<2> size, bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd); + bool SQDMULH_elt_2(bool Q, Imm<2> size, bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd); + bool SQRDMULH_elt_1(Imm<2> size, bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd); + bool SQRDMULH_elt_2(bool Q, Imm<2> size, bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd); + bool FMLA_elt_1(bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd); + bool FMLA_elt_2(bool sz, bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd); + bool FMLA_elt_3(bool Q, bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd); + bool FMLA_elt_4(bool Q, bool sz, bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd); + bool FMLS_elt_1(bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd); + bool FMLS_elt_2(bool sz, bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd); + bool FMLS_elt_3(bool Q, bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd); + bool FMLS_elt_4(bool Q, bool sz, bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd); + bool FMUL_elt_1(bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd); + bool FMUL_elt_2(bool sz, bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd); + bool FMUL_elt_3(bool Q, bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd); + bool FMUL_elt_4(bool Q, bool sz, bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd); + bool SQRDMLAH_elt_1(Imm<2> size, bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd); + bool SQRDMLAH_elt_2(bool Q, Imm<2> size, bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd); + bool SQRDMLSH_elt_1(Imm<2> size, bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd); + bool SQRDMLSH_elt_2(bool Q, Imm<2> size, bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd); + bool FMULX_elt_1(bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd); + bool FMULX_elt_2(bool sz, bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd); + bool FMULX_elt_3(bool Q, bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd); + bool FMULX_elt_4(bool Q, bool sz, bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd); + + // Data Processing - FP and SIMD - SIMD Table Lookup + bool TBL(bool Q, Vec Vm, Imm<2> len, Vec Vn, Vec Vd); + bool TBX(bool Q, Vec Vm, Imm<2> len, Vec Vn, Vec Vd); + + // Data Processing - FP and SIMD - SIMD Permute + bool UZP1(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool TRN1(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool ZIP1(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool UZP2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool TRN2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool ZIP2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + + // Data Processing - FP and SIMD - SIMD Extract + bool EXT(bool Q, Vec Vm, Imm<4> imm4, Vec Vn, Vec Vd); + + // Data Processing - FP and SIMD - SIMD Copy + bool DUP_gen(bool Q, Imm<5> imm5, Reg Rn, Vec Vd); + bool SMOV(bool Q, Imm<5> imm5, Vec Vn, Reg Rd); + bool UMOV(bool Q, Imm<5> imm5, Vec Vn, Reg Rd); + bool INS_gen(Imm<5> imm5, Reg Rn, Vec Vd); + bool INS_elt(Imm<5> imm5, Imm<4> imm4, Vec Vn, Vec Vd); + + // Data Processing - FP and SIMD - SIMD Three same + bool FMAXNM_1(bool Q, Vec Vm, Vec Vn, Vec Vd); + bool FMAXNM_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd); + bool FMLA_vec_1(bool Q, Vec Vm, Vec Vn, Vec Vd); + bool FMLA_vec_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd); + bool FADD_1(bool Q, Vec Vm, Vec Vn, Vec Vd); + bool FADD_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd); + bool FMAX_1(bool Q, Vec Vm, Vec Vn, Vec Vd); + bool FMAX_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd); + bool FMINNM_1(bool Q, Vec Vm, Vec Vn, Vec Vd); + bool FMINNM_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd); + bool FMLS_vec_1(bool Q, Vec Vm, Vec Vn, Vec Vd); + bool FMLS_vec_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd); + bool FSUB_1(bool Q, Vec Vm, Vec Vn, Vec Vd); + bool FSUB_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd); + bool FMIN_1(bool Q, Vec Vm, Vec Vn, Vec Vd); + bool FMIN_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd); + bool FMAXNMP_vec_1(bool Q, Vec Vm, Vec Vn, Vec Vd); + bool FMAXNMP_vec_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd); + bool FADDP_vec_1(bool Q, Vec Vm, Vec Vn, Vec Vd); + bool FADDP_vec_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd); + bool FMUL_vec_1(bool Q, Vec Vm, Vec Vn, Vec Vd); + bool FMUL_vec_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd); + bool FMAXP_vec_1(bool Q, Vec Vm, Vec Vn, Vec Vd); + bool FMAXP_vec_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd); + bool FDIV_1(bool Q, Vec Vm, Vec Vn, Vec Vd); + bool FDIV_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd); + bool FMINNMP_vec_1(bool Q, Vec Vm, Vec Vn, Vec Vd); + bool FMINNMP_vec_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd); + bool FMINP_vec_1(bool Q, Vec Vm, Vec Vn, Vec Vd); + bool FMINP_vec_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd); + + // Data Processing - FP and SIMD - SIMD Two-register misc + bool FRINTN_1(bool Q, Vec Vn, Vec Vd); + bool FRINTN_2(bool Q, bool sz, Vec Vn, Vec Vd); + bool FRINTM_1(bool Q, Vec Vn, Vec Vd); + bool FRINTM_2(bool Q, bool sz, Vec Vn, Vec Vd); + bool FABS_1(bool Q, Vec Vn, Vec Vd); + bool FABS_2(bool Q, bool sz, Vec Vn, Vec Vd); + bool FRINTP_1(bool Q, Vec Vn, Vec Vd); + bool FRINTP_2(bool Q, bool sz, Vec Vn, Vec Vd); + bool FRINTZ_1(bool Q, Vec Vn, Vec Vd); + bool FRINTZ_2(bool Q, bool sz, Vec Vn, Vec Vd); + bool FRINTA_1(bool Q, Vec Vn, Vec Vd); + bool FRINTA_2(bool Q, bool sz, Vec Vn, Vec Vd); + bool FRINTX_1(bool Q, Vec Vn, Vec Vd); + bool FRINTX_2(bool Q, bool sz, Vec Vn, Vec Vd); + bool FNEG_1(bool Q, Vec Vn, Vec Vd); + bool FNEG_2(bool Q, bool sz, Vec Vn, Vec Vd); + bool FRINTI_1(bool Q, Vec Vn, Vec Vd); + bool FRINTI_2(bool Q, bool sz, Vec Vn, Vec Vd); + bool FSQRT_1(bool Q, Vec Vn, Vec Vd); + bool FSQRT_2(bool Q, bool sz, Vec Vn, Vec Vd); + + // Data Processing - FP and SIMD - SIMD Three same extra + bool SDOT_vec(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool UDOT_vec(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool FCMLA_vec(bool Q, Imm<2> size, Vec Vm, Imm<2> rot, Vec Vn, Vec Vd); + bool FCADD_vec(bool Q, Imm<2> size, Vec Vm, Imm<1> rot, Vec Vn, Vec Vd); + + // Data Processing - FP and SIMD - SIMD Two register misc + bool REV64_asimd(bool Q, Imm<2> size, Vec Vn, Vec Vd); + bool REV16_asimd(bool Q, Imm<2> size, Vec Vn, Vec Vd); + bool SADDLP(bool Q, Imm<2> size, Vec Vn, Vec Vd); + bool CLS_asimd(bool Q, Imm<2> size, Vec Vn, Vec Vd); + bool CNT(bool Q, Imm<2> size, Vec Vn, Vec Vd); + bool SADALP(bool Q, Imm<2> size, Vec Vn, Vec Vd); + bool XTN(bool Q, Imm<2> size, Vec Vn, Reg Rd); + bool FCVTN(bool Q, bool sz, Vec Vn, Reg Rd); + bool FCVTL(bool Q, bool sz, Reg Rn, Vec Vd); + bool URECPE(bool Q, bool sz, Vec Vn, Vec Vd); + bool REV32_asimd(bool Q, Imm<2> size, Vec Vn, Vec Vd); + bool UADDLP(bool Q, Imm<2> size, Vec Vn, Vec Vd); + bool CLZ_asimd(bool Q, Imm<2> size, Vec Vn, Vec Vd); + bool UADALP(bool Q, Imm<2> size, Vec Vn, Vec Vd); + bool SHLL(bool Q, Imm<2> size, Reg Rn, Vec Vd); + bool NOT(bool Q, Vec Vn, Vec Vd); + bool RBIT_asimd(bool Q, Vec Vn, Vec Vd); + bool URSQRTE(bool Q, bool sz, Vec Vn, Vec Vd); + + // Data Processing - FP and SIMD - SIMD across lanes + bool SADDLV(bool Q, Imm<2> size, Vec Vn, Vec Vd); + bool SMAXV(bool Q, Imm<2> size, Vec Vn, Vec Vd); + bool SMINV(bool Q, Imm<2> size, Vec Vn, Vec Vd); + bool ADDV(bool Q, Imm<2> size, Vec Vn, Vec Vd); + bool FMAXNMV_1(bool Q, Vec Vn, Vec Vd); + bool FMAXNMV_2(bool Q, bool sz, Vec Vn, Vec Vd); + bool FMAXV_1(bool Q, Vec Vn, Vec Vd); + bool FMAXV_2(bool Q, bool sz, Vec Vn, Vec Vd); + bool FMINNMV_1(bool Q, Vec Vn, Vec Vd); + bool FMINNMV_2(bool Q, bool sz, Vec Vn, Vec Vd); + bool FMINV_1(bool Q, Vec Vn, Vec Vd); + bool FMINV_2(bool Q, bool sz, Vec Vn, Vec Vd); + bool UADDLV(bool Q, Imm<2> size, Vec Vn, Vec Vd); + bool UMAXV(bool Q, Imm<2> size, Vec Vn, Vec Vd); + bool UMINV(bool Q, Imm<2> size, Vec Vn, Vec Vd); + + // Data Processing - FP and SIMD - SIMD three different + bool SADDL(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd); + bool SADDW(bool Q, Imm<2> size, Reg Rm, Vec Vn, Vec Vd); + bool SSUBL(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd); + bool SSUBW(bool Q, Imm<2> size, Reg Rm, Vec Vn, Vec Vd); + bool ADDHN(bool Q, Imm<2> size, Vec Vm, Vec Vn, Reg Rd); + bool SABAL(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd); + bool SUBHN(bool Q, Imm<2> size, Vec Vm, Vec Vn, Reg Rd); + bool SABDL(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd); + bool SMLAL_vec(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd); + bool SMLSL_vec(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd); + bool SMULL_vec(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd); + bool PMULL(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd); + bool UADDL(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd); + bool UADDW(bool Q, Imm<2> size, Reg Rm, Vec Vn, Vec Vd); + bool USUBL(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd); + bool USUBW(bool Q, Imm<2> size, Reg Rm, Vec Vn, Vec Vd); + bool RADDHN(bool Q, Imm<2> size, Vec Vm, Vec Vn, Reg Rd); + bool UABAL(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd); + bool RSUBHN(bool Q, Imm<2> size, Vec Vm, Vec Vn, Reg Rd); + bool UABDL(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd); + bool UMLAL_vec(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd); + bool UMLSL_vec(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd); + bool UMULL_vec(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd); + + // Data Processing - FP and SIMD - SIMD three same + bool SHADD(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool SRHADD(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool SHSUB(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool SMAX(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool SMIN(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool SABD(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool SABA(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool MLA_vec(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool MUL_vec(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool SMAXP(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool SMINP(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool ADDP_vec(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool FMLAL_vec_1(bool Q, bool sz, Reg Rm, Reg Rn, Vec Vd); + bool FMLAL_vec_2(bool Q, bool sz, Reg Rm, Reg Rn, Vec Vd); + bool AND_asimd(bool Q, Vec Vm, Vec Vn, Vec Vd); + bool BIC_asimd_reg(bool Q, Vec Vm, Vec Vn, Vec Vd); + bool FMLSL_vec_1(bool Q, bool sz, Reg Rm, Reg Rn, Vec Vd); + bool FMLSL_vec_2(bool Q, bool sz, Reg Rm, Reg Rn, Vec Vd); + bool ORR_asimd_reg(bool Q, Vec Vm, Vec Vn, Vec Vd); + bool ORN_asimd(bool Q, Vec Vm, Vec Vn, Vec Vd); + bool UHADD(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool URHADD(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool UHSUB(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool UMAX(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool UMIN(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool UABD(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool UABA(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool MLS_vec(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool PMUL(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool UMAXP(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool UMINP(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); + bool EOR_asimd(bool Q, Vec Vm, Vec Vn, Vec Vd); + bool BSL(bool Q, Vec Vm, Vec Vn, Vec Vd); + bool BIT(bool Q, Vec Vm, Vec Vn, Vec Vd); + bool BIF(bool Q, Vec Vm, Vec Vn, Vec Vd); + + // Data Processing - FP and SIMD - SIMD modified immediate + bool MOVI(bool Q, bool op, Imm<1> a, Imm<1> b, Imm<1> c, Imm<4> cmode, Imm<1> d, Imm<1> e, Imm<1> f, Imm<1> g, Imm<1> h, Reg Rd); + bool ORR_asimd_imm(bool Q, Imm<1> a, Imm<1> b, Imm<1> c, Imm<1> d, Imm<1> e, Imm<1> f, Imm<1> g, Imm<1> h, Reg Rd); + bool FMOV_1(bool Q, Imm<1> a, Imm<1> b, Imm<1> c, Imm<1> d, Imm<1> e, Imm<1> f, Imm<1> g, Imm<1> h, Reg Rd); + bool FMOV_2(bool Q, bool op, Imm<1> a, Imm<1> b, Imm<1> c, Imm<1> d, Imm<1> e, Imm<1> f, Imm<1> g, Imm<1> h, Reg Rd); + bool MVNI(bool Q, Imm<1> a, Imm<1> b, Imm<1> c, Imm<4> cmode, Imm<1> d, Imm<1> e, Imm<1> f, Imm<1> g, Imm<1> h, Reg Rd); + bool BIC_imm(bool Q, Imm<1> a, Imm<1> b, Imm<1> c, Imm<1> d, Imm<1> e, Imm<1> f, Imm<1> g, Imm<1> h, Reg Rd); + + // Data Processing - FP and SIMD - SIMD Shfit by immediate + bool SHRN(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Reg Rd); + bool RSHRN(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Reg Rd); + bool SSHLL(bool Q, Imm<4> immh, Imm<3> immb, Reg Rn, Vec Vd); + bool USHLL(bool Q, Imm<4> immh, Imm<3> immb, Reg Rn, Vec Vd); + + // Data Processing - FP and SIMD - SIMD x indexed element + bool SMLAL_elt(bool Q, Imm<2> size, bool L, bool M, Vec Vm, bool H, Reg Rn, Vec Vd); + bool SMLSL_elt(bool Q, Imm<2> size, bool L, bool M, Vec Vm, bool H, Reg Rn, Vec Vd); + bool MUL_elt(bool Q, Imm<2> size, bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd); + bool SMULL_elt(bool Q, Imm<2> size, bool L, bool M, Vec Vm, bool H, Reg Rn, Vec Vd); + bool SDOT_elt(bool Q, Imm<2> size, bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd); + bool FMLAL_elt_1(bool Q, bool sz, bool L, bool M, Vec Vm, bool H, Reg Rn, Vec Vd); + bool FMLAL_elt_2(bool Q, bool sz, bool L, bool M, Vec Vm, bool H, Reg Rn, Vec Vd); + bool FMLSL_elt_1(bool Q, bool sz, bool L, bool M, Vec Vm, bool H, Reg Rn, Vec Vd); + bool FMLSL_elt_2(bool Q, bool sz, bool L, bool M, Vec Vm, bool H, Reg Rn, Vec Vd); + bool MLA_elt(bool Q, Imm<2> size, bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd); + bool UMLAL_elt(bool Q, Imm<2> size, bool L, bool M, Vec Vm, bool H, Reg Rn, Vec Vd); + bool MLS_elt(bool Q, Imm<2> size, bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd); + bool UMLSL_elt(bool Q, Imm<2> size, bool L, bool M, Vec Vm, bool H, Reg Rn, Vec Vd); + bool UMULL_elt(bool Q, Imm<2> size, bool L, bool M, Vec Vm, bool H, Reg Rn, Vec Vd); + bool UDOT_elt(bool Q, Imm<2> size, bool L, bool M, Vec Vm, bool H, Vec Vn, Vec Vd); + bool FCMLA_elt(bool Q, Imm<2> size, bool L, bool M, Vec Vm, Imm<2> rot, bool H, Vec Vn, Vec Vd); + + // Data Processing - FP and SIMD - Cryptographic three register + bool SM3TT1A(Vec Vm, Imm<2> imm2, Vec Vn, Vec Vd); + bool SM3TT1B(Vec Vm, Imm<2> imm2, Vec Vn, Vec Vd); + bool SM3TT2A(Vec Vm, Imm<2> imm2, Vec Vn, Vec Vd); + bool SM3TT2B(Vec Vm, Imm<2> imm2, Vec Vn, Vec Vd); + + // Data Processing - FP and SIMD - SHA512 three register + bool SHA512H(Vec Vm, Vec Vn, Vec Vd); + bool SHA512H2(Vec Vm, Vec Vn, Vec Vd); + bool SHA512SU1(Vec Vm, Vec Vn, Vec Vd); + bool RAX1(Vec Vm, Vec Vn, Vec Vd); + bool SM3PARTW1(Vec Vm, Vec Vn, Vec Vd); + bool SM3PARTW2(Vec Vm, Vec Vn, Vec Vd); + bool SM4EKEY(Vec Vm, Vec Vn, Vec Vd); + + // Data Processing - FP and SIMD - Cryptographic four register + bool EOR3(Vec Vm, Vec Va, Vec Vn, Vec Vd); + bool BCAX(Vec Vm, Vec Va, Vec Vn, Vec Vd); + bool SM3SS1(Vec Vm, Vec Va, Vec Vn, Vec Vd); + + // Data Processing - FP and SIMD - SHA512 two register + bool SHA512SU0(Vec Vn, Vec Vd); + bool SM4E(Vec Vn, Vec Vd); + + // Data Processing - FP and SIMD - Conversion between floating point and fixed point + bool SCVTF_float_fix(bool sf, Imm<2> type, Imm<6> scale, Reg Rn, Vec Vd); + bool UCVTF_float_fix(bool sf, Imm<2> type, Imm<6> scale, Reg Rn, Vec Vd); + bool FCVTZS_float_fix(bool sf, Imm<2> type, Imm<6> scale, Vec Vn, Reg Rd); + bool FCVTZU_float_fix(bool sf, Imm<2> type, Imm<6> scale, Vec Vn, Reg Rd); + + // Data Processing - FP and SIMD - Conversion between floating point and integer + bool FCVTNS_float(bool sf, Imm<2> type, Vec Vn, Reg Rd); + bool FCVTNU_float(bool sf, Imm<2> type, Vec Vn, Reg Rd); + bool SCVTF_float_int(bool sf, Imm<2> type, Reg Rn, Vec Vd); + bool UCVTF_float_int(bool sf, Imm<2> type, Reg Rn, Vec Vd); + bool FCVTAS_float(bool sf, Imm<2> type, Vec Vn, Reg Rd); + bool FCVTAU_float(bool sf, Imm<2> type, Vec Vn, Reg Rd); + bool FMOV_float_gen(bool sf, Imm<2> type, Vec Vn, Vec Vd); + bool FCVTPS_float(bool sf, Imm<2> type, Vec Vn, Reg Rd); + bool FCVTPU_float(bool sf, Imm<2> type, Vec Vn, Reg Rd); + bool FCVTMS_float(bool sf, Imm<2> type, Vec Vn, Reg Rd); + bool FCVTMU_float(bool sf, Imm<2> type, Vec Vn, Reg Rd); + bool FCVTZS_float_int(bool sf, Imm<2> type, Vec Vn, Reg Rd); + bool FCVTZU_float_int(bool sf, Imm<2> type, Vec Vn, Reg Rd); + bool FJCVTZS(Vec Vn, Reg Rd); + + // Data Processing - FP and SIMD - Floating point data processing + bool FMOV_float(Imm<2> type, Vec Vn, Vec Vd); + bool FABS_float(Imm<2> type, Vec Vn, Vec Vd); + bool FNEG_float(Imm<2> type, Vec Vn, Vec Vd); + bool FSQRT_float(Imm<2> type, Vec Vn, Vec Vd); + bool FCVT_float(Imm<2> type, Imm<2> opc, Vec Vn, Vec Vd); + bool FRINTN_float(Imm<2> type, Vec Vn, Vec Vd); + bool FRINTP_float(Imm<2> type, Vec Vn, Vec Vd); + bool FRINTM_float(Imm<2> type, Vec Vn, Vec Vd); + bool FRINTZ_float(Imm<2> type, Vec Vn, Vec Vd); + bool FRINTA_float(Imm<2> type, Vec Vn, Vec Vd); + bool FRINTX_float(Imm<2> type, Vec Vn, Vec Vd); + bool FRINTI_float(Imm<2> type, Vec Vn, Vec Vd); + + // Data Processing - FP and SIMD - Floating point compare + bool FCMP_float(Imm<2> type, Vec Vm, Vec Vn); + bool FCMPE_float(Imm<2> type, Vec Vm, Vec Vn); + + // Data Processing - FP and SIMD - Floating point immediate + bool FMOV_float_imm(Imm<2> type, Imm<8> imm8, Vec Vd); + + // Data Processing - FP and SIMD - Floating point conditional compare + bool FCCMP_float(Imm<2> type, Vec Vm, Cond cond, Vec Vn, Imm<4> nzcv); + bool FCCMPE_float(Imm<2> type, Vec Vm, Cond cond, Vec Vn, Imm<4> nzcv); + + // Data Processing - FP and SIMD - Floating point data processing two register + bool FMUL_float(Imm<2> type, Vec Vm, Vec Vn, Vec Vd); + bool FDIV_float(Imm<2> type, Vec Vm, Vec Vn, Vec Vd); + bool FADD_float(Imm<2> type, Vec Vm, Vec Vn, Vec Vd); + bool FSUB_float(Imm<2> type, Vec Vm, Vec Vn, Vec Vd); + bool FMAX_float(Imm<2> type, Vec Vm, Vec Vn, Vec Vd); + bool FMIN_float(Imm<2> type, Vec Vm, Vec Vn, Vec Vd); + bool FMAXNM_float(Imm<2> type, Vec Vm, Vec Vn, Vec Vd); + bool FMINNM_float(Imm<2> type, Vec Vm, Vec Vn, Vec Vd); + bool FNMUL_float(Imm<2> type, Vec Vm, Vec Vn, Vec Vd); + + // Data Processing - FP and SIMD - Floating point conditional select + bool FCSEL_float(Imm<2> type, Vec Vm, Cond cond, Vec Vn, Vec Vd); + + // Data Processing - FP and SIMD - Floating point data processing three register + bool FMADD_float(Imm<2> type, Vec Vm, Vec Va, Vec Vn, Vec Vd); + bool FMSUB_float(Imm<2> type, Vec Vm, Vec Va, Vec Vn, Vec Vd); + bool FNMADD_float(Imm<2> type, Vec Vm, Vec Va, Vec Vn, Vec Vd); + bool FNMSUB_float(Imm<2> type, Vec Vm, Vec Va, Vec Vn, Vec Vd); +}; + +} // namespace A64 +} // namespace Dynarmic \ No newline at end of file diff --git a/src/frontend/A64/translate/translate.cpp b/src/frontend/A64/translate/translate.cpp new file mode 100644 index 00000000..8e4ba7bc --- /dev/null +++ b/src/frontend/A64/translate/translate.cpp @@ -0,0 +1,21 @@ +/* This file is part of the dynarmic project. + * Copyright (c) 2018 MerryMage + * This software may be used and distributed according to the terms of the GNU + * General Public License version 2 or any later version. + */ + +#include "frontend/A64/location_descriptor.h" +#include "frontend/A64/translate/impl/impl.h" +#include "frontend/A64/translate/translate.h" +#include "frontend/ir/basic_block.h" + +namespace Dynarmic { +namespace A64 { + +IR::Block Translate(LocationDescriptor descriptor, MemoryReadCodeFuncType /*memory_read_code*/) { + // TODO + return IR::Block{descriptor}; +} + +} // namespace A64 +} // namespace Dynarmic diff --git a/src/frontend/A64/translate/translate.h b/src/frontend/A64/translate/translate.h new file mode 100644 index 00000000..9e8fc710 --- /dev/null +++ b/src/frontend/A64/translate/translate.h @@ -0,0 +1,31 @@ +/* This file is part of the dynarmic project. + * Copyright (c) 2018 MerryMage + * This software may be used and distributed according to the terms of the GNU + * General Public License version 2 or any later version. + */ +#pragma once + +#include "common/common_types.h" + +namespace Dynarmic { + +namespace IR { +class Block; +} // namespace IR + +namespace A64 { + +class LocationDescriptor; + +using MemoryReadCodeFuncType = u32 (*)(u64 vaddr); + +/** + * This function translates instructions in memory into our intermediate representation. + * @param descriptor The starting location of the basic block. Includes information like PC, Thumb state, &c. + * @param memory_read_code The function we should use to read emulated memory. + * @return A translated basic block in the intermediate representation. + */ +IR::Block Translate(LocationDescriptor descriptor, MemoryReadCodeFuncType memory_read_code); + +} // namespace A64 +} // namespace Dynarmic diff --git a/src/frontend/A64/types.cpp b/src/frontend/A64/types.cpp new file mode 100644 index 00000000..72b9ca10 --- /dev/null +++ b/src/frontend/A64/types.cpp @@ -0,0 +1,46 @@ +/* This file is part of the dynarmic project. + * Copyright (c) 2018 MerryMage + * This software may be used and distributed according to the terms of the GNU + * General Public License version 2 or any later version. + */ + +#include +#include + +#include + +#include "common/bit_util.h" +#include "frontend/A64/types.h" + +namespace Dynarmic { +namespace A64 { + +const char* CondToString(Cond cond) { + constexpr std::array cond_strs = { + "eq", "ne", "hs", "lo", "mi", "pl", "vs", "vc", "hi", "ls", "ge", "lt", "gt", "le", "al", "nv" + }; + return cond_strs.at(static_cast(cond)); +} + +std::string RegToString(Reg reg) { + if (reg == Reg::R31) + return "sp|zr"; + return fmt::format("r{}", static_cast(reg)); +} + +std::string VecToString(Vec vec) { + return fmt::format("v{}", static_cast(vec)); +} + +std::ostream& operator<<(std::ostream& o, Reg reg) { + o << RegToString(reg); + return o; +} + +std::ostream& operator<<(std::ostream& o, Vec vec) { + o << VecToString(vec); + return o; +} + +} // namespace A64 +} // namespace Dynarmic diff --git a/src/frontend/A64/types.h b/src/frontend/A64/types.h new file mode 100644 index 00000000..a2c71e1b --- /dev/null +++ b/src/frontend/A64/types.h @@ -0,0 +1,75 @@ +/* This file is part of the dynarmic project. + * Copyright (c) 2018 MerryMage + * This software may be used and distributed according to the terms of the GNU + * General Public License version 2 or any later version. + */ + +#pragma once + +#include +#include +#include + +#include "common/assert.h" +#include "common/common_types.h" +#include "frontend/ir/cond.h" + +namespace Dynarmic { +namespace A64 { + +using Cond = IR::Cond; + +enum class Reg { + R0, R1, R2, R3, R4, R5, R6, R7, + R8, R9, R10, R11, R12, R13, R14, R15, + R16, R17, R18, R19, R20, R21, R22, R23, + R24, R25, R26, R27, R28, R29, R30, R31, + LR = R30, + SP = R31, ZR = R31, +}; + +enum class Vec { + V0, V1, V2, V3, V4, V5, V6, V7, + V8, V9, V10, V11, V12, V13, V14, V15, + V16, V17, V18, V19, V20, V21, V22, V23, + V24, V25, V26, V27, V28, V29, V30, V31, +}; + +enum class ShiftType { + LSL, + LSR, + ASR, + ROR, +}; + +const char* CondToString(Cond cond); +std::string RegToString(Reg reg); +std::string VecToString(Vec vec); + +std::ostream& operator<<(std::ostream& o, Reg reg); +std::ostream& operator<<(std::ostream& o, Vec vec); + +inline size_t RegNumber(Reg reg) { + return static_cast(reg); +} + +inline size_t VecNumber(Vec vec) { + return static_cast(vec); +} + +inline Reg operator+(Reg reg, size_t number) { + size_t new_reg = static_cast(reg) + number; + ASSERT(new_reg <= 31); + + return static_cast(new_reg); +} + +inline Vec operator+(Vec vec, size_t number) { + size_t new_vec = static_cast(vec) + number; + ASSERT(new_vec <= 31); + + return static_cast(new_vec); +} + +} // namespace A64 +} // namespace Dynarmic diff --git a/src/frontend/ir/opcodes.h b/src/frontend/ir/opcodes.h index 467ea864..fc2d0e1f 100644 --- a/src/frontend/ir/opcodes.h +++ b/src/frontend/ir/opcodes.h @@ -43,7 +43,8 @@ enum class Type { U64 = 1 << 9, F32 = 1 << 10, F64 = 1 << 11, - CoprocInfo = 1 << 12, + F128 = 1 << 12, + CoprocInfo = 1 << 13, }; constexpr Type operator|(Type a, Type b) { diff --git a/src/frontend/ir/value.cpp b/src/frontend/ir/value.cpp index 49b218c1..7203e33f 100644 --- a/src/frontend/ir/value.cpp +++ b/src/frontend/ir/value.cpp @@ -23,6 +23,14 @@ Value::Value(A32::ExtReg value) : type(Type::A32ExtReg) { inner.imm_a32extregref = value; } +Value::Value(A64::Reg value) : type(Type::A64Reg) { + inner.imm_a64regref = value; +} + +Value::Value(A64::Vec value) : type(Type::A64Vec) { + inner.imm_a64vecref = value; +} + Value::Value(bool value) : type(Type::U1) { inner.imm_u1 = value; } @@ -78,6 +86,16 @@ A32::ExtReg Value::GetA32ExtRegRef() const { return inner.imm_a32extregref; } +A64::Reg Value::GetA64RegRef() const { + ASSERT(type == Type::A64Reg); + return inner.imm_a64regref; +} + +A64::Vec Value::GetA64VecRef() const { + ASSERT(type == Type::A64Vec); + return inner.imm_a64vecref; +} + Inst* Value::GetInst() const { ASSERT(type == Type::Opaque); return inner.inst; diff --git a/src/frontend/ir/value.h b/src/frontend/ir/value.h index c101ca6e..05aa5b11 100644 --- a/src/frontend/ir/value.h +++ b/src/frontend/ir/value.h @@ -9,6 +9,8 @@ #include "common/assert.h" #include "common/common_types.h" #include "frontend/A32/types.h" +#include "frontend/A64/types.h" +#include "frontend/ir/opcodes.h" namespace Dynarmic { namespace IR { @@ -25,6 +27,8 @@ public: explicit Value(Inst* value); explicit Value(A32::Reg value); explicit Value(A32::ExtReg value); + explicit Value(A64::Reg value); + explicit Value(A64::Vec value); explicit Value(bool value); explicit Value(u8 value); explicit Value(u16 value); @@ -39,6 +43,8 @@ public: Inst* GetInst() const; A32::Reg GetA32RegRef() const; A32::ExtReg GetA32ExtRegRef() const; + A64::Reg GetA64RegRef() const; + A64::Vec GetA64VecRef() const; bool GetU1() const; u8 GetU8() const; u16 GetU16() const; @@ -53,6 +59,8 @@ private: Inst* inst; // type == Type::Opaque A32::Reg imm_a32regref; A32::ExtReg imm_a32extregref; + A64::Reg imm_a64regref; + A64::Vec imm_a64vecref; bool imm_u1; u8 imm_u8; u16 imm_u16; @@ -86,6 +94,7 @@ using U32 = TypedValue; using U64 = TypedValue; using F32 = TypedValue; using F64 = TypedValue; +using F128 = TypedValue; using F32F64 = TypedValue; } // namespace IR