diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc index fae18f1c..4b694665 100644 --- a/src/frontend/A64/decoder/a64.inc +++ b/src/frontend/A64/decoder/a64.inc @@ -678,7 +678,7 @@ INST(NOT, "NOT", "0Q101 //INST(SADDL, "SADDL, SADDL2", "0Q001110zz1mmmmm000000nnnnnddddd") INST(SADDW, "SADDW, SADDW2", "0Q001110zz1mmmmm000100nnnnnddddd") //INST(SSUBL, "SSUBL, SSUBL2", "0Q001110zz1mmmmm001000nnnnnddddd") -//INST(SSUBW, "SSUBW, SSUBW2", "0Q001110zz1mmmmm001100nnnnnddddd") +INST(SSUBW, "SSUBW, SSUBW2", "0Q001110zz1mmmmm001100nnnnnddddd") //INST(ADDHN, "ADDHN, ADDHN2", "0Q001110zz1mmmmm010000nnnnnddddd") //INST(SABAL, "SABAL, SABAL2", "0Q001110zz1mmmmm010100nnnnnddddd") //INST(SUBHN, "SUBHN, SUBHN2", "0Q001110zz1mmmmm011000nnnnnddddd") diff --git a/src/frontend/A64/translate/impl/impl.h b/src/frontend/A64/translate/impl/impl.h index 2cdbc1f2..c2e3d453 100644 --- a/src/frontend/A64/translate/impl/impl.h +++ b/src/frontend/A64/translate/impl/impl.h @@ -805,7 +805,7 @@ struct TranslatorVisitor final { bool SADDL(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd); bool SADDW(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); bool SSUBL(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd); - bool SSUBW(bool Q, Imm<2> size, Reg Rm, Vec Vn, Vec Vd); + bool SSUBW(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); bool ADDHN(bool Q, Imm<2> size, Vec Vm, Vec Vn, Reg Rd); bool SABAL(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd); bool SUBHN(bool Q, Imm<2> size, Vec Vm, Vec Vn, Reg Rd); diff --git a/src/frontend/A64/translate/impl/simd_three_different.cpp b/src/frontend/A64/translate/impl/simd_three_different.cpp index e8503079..ef0c8647 100644 --- a/src/frontend/A64/translate/impl/simd_three_different.cpp +++ b/src/frontend/A64/translate/impl/simd_three_different.cpp @@ -24,6 +24,22 @@ bool TranslatorVisitor::SADDW(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { return true; } +bool TranslatorVisitor::SSUBW(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { + if (size == 0b11) { + return ReservedValue(); + } + + const size_t esize = 8 << size.ZeroExtend(); + const size_t part = Q ? 1 : 0; + + const IR::U128 operand1 = V(128, Vn); + const IR::U128 operand2 = ir.VectorSignExtend(esize, Vpart(64, Vm, part)); + const IR::U128 result = ir.VectorSub(esize * 2, operand1, operand2); + + V(128, Vd, result); + return true; +} + bool TranslatorVisitor::UADDW(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { if (size == 0b11) { return ReservedValue();