From e3d9bf55e7cb9c75986957a0b71ffc46edb5665e Mon Sep 17 00:00:00 2001 From: Lioncash Date: Sat, 7 Apr 2018 23:14:20 -0400 Subject: [PATCH] A64: Implement SRSRA (vector) --- src/frontend/A64/decoder/a64.inc | 2 +- .../A64/translate/impl/simd_shift_by_immediate.cpp | 13 +++++++++++++ 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc index e8a306f8..88d66bc2 100644 --- a/src/frontend/A64/decoder/a64.inc +++ b/src/frontend/A64/decoder/a64.inc @@ -792,7 +792,7 @@ INST(UnallocatedEncoding, "Unallocated SIMD modified immediate", "0--01 INST(SSHR_2, "SSHR", "0Q0011110IIIIiii000001nnnnnddddd") INST(SSRA_2, "SSRA", "0Q0011110IIIIiii000101nnnnnddddd") INST(SRSHR_2, "SRSHR", "0Q0011110IIIIiii001001nnnnnddddd") -//INST(SRSRA_2, "SRSRA", "0Q0011110IIIIiii001101nnnnnddddd") +INST(SRSRA_2, "SRSRA", "0Q0011110IIIIiii001101nnnnnddddd") INST(SHL_2, "SHL", "0Q0011110IIIIiii010101nnnnnddddd") //INST(SQSHL_imm_2, "SQSHL (immediate)", "0Q0011110IIIIiii011101nnnnnddddd") INST(SHRN, "SHRN, SHRN2", "0Q0011110IIIIiii100001nnnnnddddd") diff --git a/src/frontend/A64/translate/impl/simd_shift_by_immediate.cpp b/src/frontend/A64/translate/impl/simd_shift_by_immediate.cpp index 8bba5924..48ead849 100644 --- a/src/frontend/A64/translate/impl/simd_shift_by_immediate.cpp +++ b/src/frontend/A64/translate/impl/simd_shift_by_immediate.cpp @@ -80,6 +80,19 @@ bool TranslatorVisitor::SRSHR_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd return true; } +bool TranslatorVisitor::SRSRA_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { + if (immh == 0b0000) { + return DecodeError(); + } + + if (!Q && immh.Bit<3>()) { + return ReservedValue(); + } + + SignedRoundingShiftRight(*this, Q, immh, immb, Vn, Vd, ShiftExtraBehavior::Accumulate); + return true; +} + bool TranslatorVisitor::SSRA_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { if (immh == 0b0000) { return DecodeError();