diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc
index 9400bdf0..3e110aef 100644
--- a/src/frontend/A64/decoder/a64.inc
+++ b/src/frontend/A64/decoder/a64.inc
@@ -425,7 +425,7 @@ INST(FCVTZS_int_2,           "FCVTZS (vector, integer)",                  "01011
 //INST(FRECPE_1,               "FRECPE",                                    "0101111011111001110110nnnnnddddd")
 INST(FRECPE_2,               "FRECPE",                                    "010111101z100001110110nnnnnddddd")
 //INST(FRECPX_1,               "FRECPX",                                    "0101111011111001111110nnnnnddddd")
-//INST(FRECPX_2,               "FRECPX",                                    "010111101z100001111110nnnnnddddd")
+INST(FRECPX_2,               "FRECPX",                                    "010111101z100001111110nnnnnddddd")
 //INST(FCVTNU_1,               "FCVTNU (vector)",                           "0111111001111001101010nnnnnddddd")
 INST(FCVTNU_2,               "FCVTNU (vector)",                           "011111100z100001101010nnnnnddddd")
 //INST(FCVTMU_1,               "FCVTMU (vector)",                           "0111111001111001101110nnnnnddddd")
diff --git a/src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp b/src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp
index ebb621c1..b8283d7c 100644
--- a/src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp
+++ b/src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp
@@ -170,6 +170,16 @@ bool TranslatorVisitor::FRECPE_2(bool sz, Vec Vn, Vec Vd) {
     return true;
 }
 
+bool TranslatorVisitor::FRECPX_2(bool sz, Vec Vn, Vec Vd) {
+    const size_t esize = sz ? 64 : 32;
+
+    const IR::U32U64 operand = V_scalar(esize, Vn);
+    const IR::U32U64 result = ir.FPRecipExponent(operand);
+
+    V_scalar(esize, Vd, result);
+    return true;
+}
+
 bool TranslatorVisitor::FRSQRTE_2(bool sz, Vec Vn, Vec Vd) {
     const size_t esize = sz ? 64 : 32;