From e4c259d69f254c66f4870bfd94a4071428c78e6e Mon Sep 17 00:00:00 2001 From: Lioncash Date: Sat, 23 Mar 2019 10:02:51 -0400 Subject: [PATCH] frontend/ir_emitter: Add half->{single, double} and {double, single}->half conversion opcodes --- src/backend/x64/emit_x64_floating_point.cpp | 44 +++++++++++++++++++++ src/frontend/ir/ir_emitter.cpp | 16 ++++++++ src/frontend/ir/ir_emitter.h | 4 ++ src/frontend/ir/microinstruction.cpp | 4 ++ src/frontend/ir/opcodes.inc | 4 ++ 5 files changed, 72 insertions(+) diff --git a/src/backend/x64/emit_x64_floating_point.cpp b/src/backend/x64/emit_x64_floating_point.cpp index 028c281d..d59ddbbd 100644 --- a/src/backend/x64/emit_x64_floating_point.cpp +++ b/src/backend/x64/emit_x64_floating_point.cpp @@ -1036,6 +1036,28 @@ void EmitX64::EmitFPCompare64(EmitContext& ctx, IR::Inst* inst) { ctx.reg_alloc.DefineValue(inst, nzcv); } +void EmitX64::EmitFPHalfToDouble(EmitContext& ctx, IR::Inst* inst) { + auto args = ctx.reg_alloc.GetArgumentInfo(inst); + const auto rounding_mode = static_cast(args[1].GetImmediateU8()); + + ctx.reg_alloc.HostCall(inst, args[0]); + code.mov(code.ABI_PARAM2.cvt32(), ctx.FPCR()); + code.mov(code.ABI_PARAM3.cvt32(), static_cast(rounding_mode)); + code.lea(code.ABI_PARAM4, code.ptr[code.r15 + code.GetJitStateInfo().offsetof_fpsr_exc]); + code.CallFunction(&FP::FPConvert); +} + +void EmitX64::EmitFPHalfToSingle(EmitContext& ctx, IR::Inst* inst) { + auto args = ctx.reg_alloc.GetArgumentInfo(inst); + const auto rounding_mode = static_cast(args[1].GetImmediateU8()); + + ctx.reg_alloc.HostCall(inst, args[0]); + code.mov(code.ABI_PARAM2.cvt32(), ctx.FPCR()); + code.mov(code.ABI_PARAM3.cvt32(), static_cast(rounding_mode)); + code.lea(code.ABI_PARAM4, code.ptr[code.r15 + code.GetJitStateInfo().offsetof_fpsr_exc]); + code.CallFunction(&FP::FPConvert); +} + void EmitX64::EmitFPSingleToDouble(EmitContext& ctx, IR::Inst* inst) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); const auto rounding_mode = static_cast(args[1].GetImmediateU8()); @@ -1058,6 +1080,28 @@ void EmitX64::EmitFPSingleToDouble(EmitContext& ctx, IR::Inst* inst) { } } +void EmitX64::EmitFPSingleToHalf(EmitContext& ctx, IR::Inst* inst) { + auto args = ctx.reg_alloc.GetArgumentInfo(inst); + const auto rounding_mode = static_cast(args[1].GetImmediateU8()); + + ctx.reg_alloc.HostCall(inst, args[0]); + code.mov(code.ABI_PARAM2.cvt32(), ctx.FPCR()); + code.mov(code.ABI_PARAM3.cvt32(), static_cast(rounding_mode)); + code.lea(code.ABI_PARAM4, code.ptr[code.r15 + code.GetJitStateInfo().offsetof_fpsr_exc]); + code.CallFunction(&FP::FPConvert); +} + +void EmitX64::EmitFPDoubleToHalf(EmitContext& ctx, IR::Inst* inst) { + auto args = ctx.reg_alloc.GetArgumentInfo(inst); + const auto rounding_mode = static_cast(args[1].GetImmediateU8()); + + ctx.reg_alloc.HostCall(inst, args[0]); + code.mov(code.ABI_PARAM2.cvt32(), ctx.FPCR()); + code.mov(code.ABI_PARAM3.cvt32(), static_cast(rounding_mode)); + code.lea(code.ABI_PARAM4, code.ptr[code.r15 + code.GetJitStateInfo().offsetof_fpsr_exc]); + code.CallFunction(&FP::FPConvert); +} + void EmitX64::EmitFPDoubleToSingle(EmitContext& ctx, IR::Inst* inst) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); const auto rounding_mode = static_cast(args[1].GetImmediateU8()); diff --git a/src/frontend/ir/ir_emitter.cpp b/src/frontend/ir/ir_emitter.cpp index 35c8d07b..1da47e4f 100644 --- a/src/frontend/ir/ir_emitter.cpp +++ b/src/frontend/ir/ir_emitter.cpp @@ -1955,14 +1955,30 @@ U32U64 IREmitter::FPSub(const U32U64& a, const U32U64& b, bool fpcr_controlled) } } +U16 IREmitter::FPDoubleToHalf(const U64& a, FP::RoundingMode rounding) { + return Inst(Opcode::FPDoubleToHalf, a, Imm8(static_cast(rounding))); +} + U32 IREmitter::FPDoubleToSingle(const U64& a, FP::RoundingMode rounding) { return Inst(Opcode::FPDoubleToSingle, a, Imm8(static_cast(rounding))); } +U64 IREmitter::FPHalfToDouble(const U16& a, FP::RoundingMode rounding) { + return Inst(Opcode::FPHalfToDouble, a, Imm8(static_cast(rounding))); +} + +U32 IREmitter::FPHalfToSingle(const U16& a, FP::RoundingMode rounding) { + return Inst(Opcode::FPHalfToSingle, a, Imm8(static_cast(rounding))); +} + U64 IREmitter::FPSingleToDouble(const U32& a, FP::RoundingMode rounding) { return Inst(Opcode::FPSingleToDouble, a, Imm8(static_cast(rounding))); } +U16 IREmitter::FPSingleToHalf(const U32& a, FP::RoundingMode rounding) { + return Inst(Opcode::FPSingleToHalf, a, Imm8(static_cast(rounding))); +} + U32 IREmitter::FPToFixedS32(const U32U64& a, size_t fbits, FP::RoundingMode rounding) { ASSERT(fbits <= 32); const Opcode opcode = a.GetType() == Type::U32 ? Opcode::FPSingleToFixedS32 : Opcode::FPDoubleToFixedS32; diff --git a/src/frontend/ir/ir_emitter.h b/src/frontend/ir/ir_emitter.h index 0e29d716..f4533801 100644 --- a/src/frontend/ir/ir_emitter.h +++ b/src/frontend/ir/ir_emitter.h @@ -312,7 +312,11 @@ public: U32U64 FPRSqrtStepFused(const U32U64& a, const U32U64& b); U32U64 FPSqrt(const U32U64& a); U32U64 FPSub(const U32U64& a, const U32U64& b, bool fpcr_controlled); + U16 FPDoubleToHalf(const U64& a, FP::RoundingMode rounding); U32 FPDoubleToSingle(const U64& a, FP::RoundingMode rounding); + U64 FPHalfToDouble(const U16& a, FP::RoundingMode rounding); + U32 FPHalfToSingle(const U16& a, FP::RoundingMode rounding); + U16 FPSingleToHalf(const U32& a, FP::RoundingMode rounding); U64 FPSingleToDouble(const U32& a, FP::RoundingMode rounding); U32 FPToFixedS32(const U32U64& a, size_t fbits, FP::RoundingMode rounding); U64 FPToFixedS64(const U32U64& a, size_t fbits, FP::RoundingMode rounding); diff --git a/src/frontend/ir/microinstruction.cpp b/src/frontend/ir/microinstruction.cpp index 3055d2fd..46d5fb87 100644 --- a/src/frontend/ir/microinstruction.cpp +++ b/src/frontend/ir/microinstruction.cpp @@ -288,7 +288,11 @@ bool Inst::ReadsFromAndWritesToFPSRCumulativeExceptionBits() const { case Opcode::FPSqrt64: case Opcode::FPSub32: case Opcode::FPSub64: + case Opcode::FPHalfToDouble: + case Opcode::FPHalfToSingle: case Opcode::FPSingleToDouble: + case Opcode::FPSingleToHalf: + case Opcode::FPDoubleToHalf: case Opcode::FPDoubleToSingle: case Opcode::FPDoubleToFixedS32: case Opcode::FPDoubleToFixedS64: diff --git a/src/frontend/ir/opcodes.inc b/src/frontend/ir/opcodes.inc index ca87994a..734a0934 100644 --- a/src/frontend/ir/opcodes.inc +++ b/src/frontend/ir/opcodes.inc @@ -503,7 +503,11 @@ OPCODE(FPSub32, U32, U32, OPCODE(FPSub64, U64, U64, U64 ) // Floating-point conversions +OPCODE(FPHalfToDouble, U64, U16, U8 ) +OPCODE(FPHalfToSingle, U32, U16, U8 ) OPCODE(FPSingleToDouble, U64, U32, U8 ) +OPCODE(FPSingleToHalf, U16, U32, U8 ) +OPCODE(FPDoubleToHalf, U16, U64, U8 ) OPCODE(FPDoubleToSingle, U32, U64, U8 ) OPCODE(FPDoubleToFixedS32, U32, U64, U8, U8 ) OPCODE(FPDoubleToFixedS64, U64, U64, U8, U8 )