diff --git a/src/frontend/A32/decoder/thumb32.inc b/src/frontend/A32/decoder/thumb32.inc
index 6ba27249..9083b48a 100644
--- a/src/frontend/A32/decoder/thumb32.inc
+++ b/src/frontend/A32/decoder/thumb32.inc
@@ -38,7 +38,7 @@ INST(thumb32_MVN_reg,        "MVN (reg)",                "11101010011S11110vvvdd
 INST(thumb32_ORN_reg,        "ORN (reg)",                "11101010011Snnnn0vvvddddvvttmmmm")
 INST(thumb32_TEQ_reg,        "TEQ (reg)",                "111010101001nnnn0vvv1111vvttmmmm")
 INST(thumb32_EOR_reg,        "EOR (reg)",                "11101010100Snnnn0vvvddddvvttmmmm")
-//INST(thumb32_PKH,            "PKH",                      "11101010110---------------------")
+INST(thumb32_PKH,            "PKH",                      "111010101100nnnn0vvvddddvvt0mmmm")
 //INST(thumb32_CMN_reg,        "CMN (reg)",                "111010110001--------1111--------")
 //INST(thumb32_ADD_reg,        "ADD (reg)",                "11101011000---------------------")
 //INST(thumb32_ADC_reg,        "ADC (reg)",                "11101011010---------------------")
diff --git a/src/frontend/A32/translate/impl/thumb32_data_processing_shifted_register.cpp b/src/frontend/A32/translate/impl/thumb32_data_processing_shifted_register.cpp
index c9090100..6992d608 100644
--- a/src/frontend/A32/translate/impl/thumb32_data_processing_shifted_register.cpp
+++ b/src/frontend/A32/translate/impl/thumb32_data_processing_shifted_register.cpp
@@ -155,4 +155,19 @@ bool ThumbTranslatorVisitor::thumb32_EOR_reg(bool S, Reg n, Imm<3> imm3, Reg d,
     return true;
 }
 
+bool ThumbTranslatorVisitor::thumb32_PKH(Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, Imm<1> tb, Reg m) {
+    const ShiftType type = concatenate(tb, Imm<1>{0}).ZeroExtend<ShiftType>();
+
+    if (d == Reg::PC || n == Reg::PC || m == Reg::PC) {
+        return UnpredictableInstruction();
+    }
+
+    const auto operand2 = EmitImmShift(ir.GetRegister(m), type, imm3, imm2, ir.GetCFlag()).result;
+    const auto lower = ir.And((tb == 1) ? operand2 : ir.GetRegister(n), ir.Imm32(0x0000FFFF));
+    const auto upper = ir.And((tb == 1) ? ir.GetRegister(n) : operand2, ir.Imm32(0xFFFF0000));
+    const auto result = ir.Or(upper, lower);
+    ir.SetRegister(d, result);
+    return true;
+}
+
 } // namespace Dynarmic::A32
diff --git a/src/frontend/A32/translate/impl/translate_thumb.h b/src/frontend/A32/translate/impl/translate_thumb.h
index 2acf6e65..afce0701 100644
--- a/src/frontend/A32/translate/impl/translate_thumb.h
+++ b/src/frontend/A32/translate/impl/translate_thumb.h
@@ -181,6 +181,7 @@ struct ThumbTranslatorVisitor final {
     bool thumb32_ORN_reg(bool S, Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, ShiftType type, Reg m);
     bool thumb32_TEQ_reg(Reg n, Imm<3> imm3, Imm<2> imm2, ShiftType type, Reg m);
     bool thumb32_EOR_reg(bool S, Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, ShiftType type, Reg m);
+    bool thumb32_PKH(Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, Imm<1> tb, Reg m);
 
     // thumb32 data processing (modified immediate) instructions
     bool thumb32_TST_imm(Imm<1> i, Reg n, Imm<3> imm3, Imm<8> imm8);