From e8b0f25dffa32b06ffb89330f89c253b2f27855f Mon Sep 17 00:00:00 2001 From: Lioncash Date: Sat, 15 Sep 2018 20:30:29 -0400 Subject: [PATCH] A64: Implement SQSHL's vector register variant --- src/frontend/A64/decoder/a64.inc | 2 +- .../A64/translate/impl/simd_three_same.cpp | 16 ++++++++++++++++ 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc index bb42f89b..7c8c065b 100644 --- a/src/frontend/A64/decoder/a64.inc +++ b/src/frontend/A64/decoder/a64.inc @@ -709,7 +709,7 @@ INST(SQSUB_2, "SQSUB", "0Q001 INST(CMGT_reg_2, "CMGT (register)", "0Q001110zz1mmmmm001101nnnnnddddd") INST(CMGE_reg_2, "CMGE (register)", "0Q001110zz1mmmmm001111nnnnnddddd") INST(SSHL_2, "SSHL", "0Q001110zz1mmmmm010001nnnnnddddd") -//INST(SQSHL_reg_2, "SQSHL (register)", "0Q001110zz1mmmmm010011nnnnnddddd") +INST(SQSHL_reg_2, "SQSHL (register)", "0Q001110zz1mmmmm010011nnnnnddddd") INST(SRSHL_2, "SRSHL", "0Q001110zz1mmmmm010101nnnnnddddd") //INST(SQRSHL_2, "SQRSHL", "0Q001110zz1mmmmm010111nnnnnddddd") INST(SMAX, "SMAX", "0Q001110zz1mmmmm011001nnnnnddddd") diff --git a/src/frontend/A64/translate/impl/simd_three_same.cpp b/src/frontend/A64/translate/impl/simd_three_same.cpp index f9c35262..1f560c6f 100644 --- a/src/frontend/A64/translate/impl/simd_three_same.cpp +++ b/src/frontend/A64/translate/impl/simd_three_same.cpp @@ -778,6 +778,22 @@ bool TranslatorVisitor::CMTST_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { return true; } +bool TranslatorVisitor::SQSHL_reg_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { + if (size == 0b11 && !Q) { + return ReservedValue(); + } + + const size_t esize = 8 << size.ZeroExtend(); + const size_t datasize = Q ? 128 : 64; + + const IR::U128 operand1 = V(datasize, Vn); + const IR::U128 operand2 = V(datasize, Vm); + const IR::U128 result = ir.VectorSignedSaturatedShiftLeft(esize, operand1, operand2); + + V(datasize, Vd, result); + return true; +} + bool TranslatorVisitor::SRSHL_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { return RoundingShiftLeft(*this, Q, size, Vm, Vn, Vd, Signedness::Signed); }