From eb332b383614dbac70784ab0bcc890148c2afb1d Mon Sep 17 00:00:00 2001 From: Lioncash Date: Sat, 16 May 2020 13:36:02 -0400 Subject: [PATCH] asimd_three_same: Unify BitwiseInstructionWithDst with BitwiseInstruction Now that all bitwise instructions are implemented, we can unify all of them together using if constexpr. --- .../A32/translate/impl/asimd_three_same.cpp | 56 +++++++------------ 1 file changed, 21 insertions(+), 35 deletions(-) diff --git a/src/frontend/A32/translate/impl/asimd_three_same.cpp b/src/frontend/A32/translate/impl/asimd_three_same.cpp index f094673b..b0696dec 100644 --- a/src/frontend/A32/translate/impl/asimd_three_same.cpp +++ b/src/frontend/A32/translate/impl/asimd_three_same.cpp @@ -13,7 +13,7 @@ ExtReg ToExtReg(size_t base, bool bit) { return ExtReg::D0 + (base + (bit ? 16 : 0)); } -template +template bool BitwiseInstruction(ArmTranslatorVisitor& v, bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm, Callable fn) { if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) { return v.UndefinedInstruction(); @@ -25,32 +25,18 @@ bool BitwiseInstruction(ArmTranslatorVisitor& v, bool D, size_t Vn, size_t Vd, b const size_t regs = Q ? 2 : 1; for (size_t i = 0; i < regs; i++) { - const IR::U32U64 reg_m = v.ir.GetExtendedRegister(m + i); - const IR::U32U64 reg_n = v.ir.GetExtendedRegister(n + i); - const IR::U32U64 result = fn(reg_n, reg_m); - v.ir.SetExtendedRegister(d + i, result); - } - - return true; -} - -template -bool BitwiseInstructionWithDst(ArmTranslatorVisitor& v, bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm, Callable fn) { - if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) { - return v.UndefinedInstruction(); - } - - const auto d = ToExtReg(Vd, D); - const auto m = ToExtReg(Vm, M); - const auto n = ToExtReg(Vn, N); - const size_t regs = Q ? 2 : 1; - - for (size_t i = 0; i < regs; i++) { - const IR::U32U64 reg_d = v.ir.GetExtendedRegister(d + i); - const IR::U32U64 reg_m = v.ir.GetExtendedRegister(m + i); - const IR::U32U64 reg_n = v.ir.GetExtendedRegister(n + i); - const IR::U32U64 result = fn(reg_d, reg_n, reg_m); - v.ir.SetExtendedRegister(d + i, result); + if constexpr (WithDst) { + const IR::U32U64 reg_d = v.ir.GetExtendedRegister(d + i); + const IR::U32U64 reg_m = v.ir.GetExtendedRegister(m + i); + const IR::U32U64 reg_n = v.ir.GetExtendedRegister(n + i); + const IR::U32U64 result = fn(reg_d, reg_n, reg_m); + v.ir.SetExtendedRegister(d + i, result); + } else { + const IR::U32U64 reg_m = v.ir.GetExtendedRegister(m + i); + const IR::U32U64 reg_n = v.ir.GetExtendedRegister(n + i); + const IR::U32U64 result = fn(reg_n, reg_m); + v.ir.SetExtendedRegister(d + i, result); + } } return true; @@ -58,49 +44,49 @@ bool BitwiseInstructionWithDst(ArmTranslatorVisitor& v, bool D, size_t Vn, size_ } // Anonymous namespace bool ArmTranslatorVisitor::asimd_VAND_reg(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) { - return BitwiseInstruction(*this, D, Vn, Vd, N, Q, M, Vm, [this](const auto& reg_n, const auto& reg_m) { + return BitwiseInstruction(*this, D, Vn, Vd, N, Q, M, Vm, [this](const auto& reg_n, const auto& reg_m) { return ir.And(reg_n, reg_m); }); } bool ArmTranslatorVisitor::asimd_VBIC_reg(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) { - return BitwiseInstruction(*this, D, Vn, Vd, N, Q, M, Vm, [this](const auto& reg_n, const auto& reg_m) { + return BitwiseInstruction(*this, D, Vn, Vd, N, Q, M, Vm, [this](const auto& reg_n, const auto& reg_m) { return ir.And(reg_n, ir.Not(reg_m)); }); } bool ArmTranslatorVisitor::asimd_VORR_reg(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) { - return BitwiseInstruction(*this, D, Vn, Vd, N, Q, M, Vm, [this](const auto& reg_n, const auto& reg_m) { + return BitwiseInstruction(*this, D, Vn, Vd, N, Q, M, Vm, [this](const auto& reg_n, const auto& reg_m) { return ir.Or(reg_n, reg_m); }); } bool ArmTranslatorVisitor::asimd_VORN_reg(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) { - return BitwiseInstruction(*this, D, Vn, Vd, N, Q, M, Vm, [this](const auto& reg_n, const auto& reg_m) { + return BitwiseInstruction(*this, D, Vn, Vd, N, Q, M, Vm, [this](const auto& reg_n, const auto& reg_m) { return ir.Or(reg_n, ir.Not(reg_m)); }); } bool ArmTranslatorVisitor::asimd_VEOR_reg(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) { - return BitwiseInstruction(*this, D, Vn, Vd, N, Q, M, Vm, [this](const auto& reg_n, const auto& reg_m) { + return BitwiseInstruction(*this, D, Vn, Vd, N, Q, M, Vm, [this](const auto& reg_n, const auto& reg_m) { return ir.Eor(reg_n, reg_m); }); } bool ArmTranslatorVisitor::asimd_VBSL(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) { - return BitwiseInstructionWithDst(*this, D, Vn, Vd, N, Q, M, Vm, [this](const auto& reg_d, const auto& reg_n, const auto& reg_m) { + return BitwiseInstruction(*this, D, Vn, Vd, N, Q, M, Vm, [this](const auto& reg_d, const auto& reg_n, const auto& reg_m) { return ir.Or(ir.And(reg_n, reg_d), ir.And(reg_m, ir.Not(reg_d))); }); } bool ArmTranslatorVisitor::asimd_VBIT(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) { - return BitwiseInstructionWithDst(*this, D, Vn, Vd, N, Q, M, Vm, [this](const auto& reg_d, const auto& reg_n, const auto& reg_m) { + return BitwiseInstruction(*this, D, Vn, Vd, N, Q, M, Vm, [this](const auto& reg_d, const auto& reg_n, const auto& reg_m) { return ir.Or(ir.And(reg_n, reg_m), ir.And(reg_d, ir.Not(reg_m))); }); } bool ArmTranslatorVisitor::asimd_VBIF(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) { - return BitwiseInstructionWithDst(*this, D, Vn, Vd, N, Q, M, Vm, [this](const auto& reg_d, const auto& reg_n, const auto& reg_m) { + return BitwiseInstruction(*this, D, Vn, Vd, N, Q, M, Vm, [this](const auto& reg_d, const auto& reg_n, const auto& reg_m) { return ir.Or(ir.And(reg_d, reg_m), ir.And(reg_n, ir.Not(reg_m))); }); }