From ed0b84da707a3dee22319c464bf46cd5b1ed20dc Mon Sep 17 00:00:00 2001
From: Lioncash <mathew1800@gmail.com>
Date: Mon, 23 Apr 2018 09:45:30 -0400
Subject: [PATCH] A64: Implement CMLE (zero)'s vector variant

---
 src/frontend/A64/decoder/a64.inc              |  2 +-
 .../translate/impl/simd_two_register_misc.cpp | 20 +++++++++++++++++++
 2 files changed, 21 insertions(+), 1 deletion(-)

diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc
index ac9692f5..c93ed0df 100644
--- a/src/frontend/A64/decoder/a64.inc
+++ b/src/frontend/A64/decoder/a64.inc
@@ -619,7 +619,7 @@ INST(REV32_asimd,            "REV32 (vector)",                            "0Q101
 //INST(UADALP,                 "UADALP",                                    "0Q101110zz100000011010nnnnnddddd")
 //INST(SQNEG_2,                "SQNEG",                                     "0Q101110zz100000011110nnnnnddddd")
 INST(CMGE_zero_2,            "CMGE (zero)",                               "0Q101110zz100000100010nnnnnddddd")
-//INST(CMLE_2,                 "CMLE (zero)",                               "0Q101110zz100000100110nnnnnddddd")
+INST(CMLE_2,                 "CMLE (zero)",                               "0Q101110zz100000100110nnnnnddddd")
 INST(NEG_2,                  "NEG (vector)",                              "0Q101110zz100000101110nnnnnddddd")
 //INST(SQXTUN_2,               "SQXTUN, SQXTUN2",                           "0Q101110zz100001001010nnnnnddddd")
 //INST(SHLL,                   "SHLL, SHLL2",                               "0Q101110zz100001001110nnnnnddddd")
diff --git a/src/frontend/A64/translate/impl/simd_two_register_misc.cpp b/src/frontend/A64/translate/impl/simd_two_register_misc.cpp
index c4d5ed4a..421f9b7e 100644
--- a/src/frontend/A64/translate/impl/simd_two_register_misc.cpp
+++ b/src/frontend/A64/translate/impl/simd_two_register_misc.cpp
@@ -75,6 +75,26 @@ bool TranslatorVisitor::CMEQ_zero_2(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
     return true;
 }
 
+bool TranslatorVisitor::CMLE_2(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
+    if (size == 0b11 && !Q) {
+        return ReservedValue();
+    }
+
+    const size_t esize = 8 << size.ZeroExtend<size_t>();
+    const size_t datasize = Q ? 128 : 64;
+
+    const IR::U128 operand = V(datasize, Vn);
+    const IR::U128 zero = ir.ZeroVector();
+
+    IR::U128 result = ir.VectorLessEqualSigned(esize, operand, zero);
+    if (datasize == 64) {
+        result = ir.VectorZeroUpper(result);
+    }
+
+    V(datasize, Vd, result);
+    return true;
+}
+
 bool TranslatorVisitor::ABS_2(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
     if (!Q && size == 0b11) {
         return ReservedValue();