diff --git a/src/frontend/A32/decoder/thumb32.inc b/src/frontend/A32/decoder/thumb32.inc index 3b58d50e..8b8b8a99 100644 --- a/src/frontend/A32/decoder/thumb32.inc +++ b/src/frontend/A32/decoder/thumb32.inc @@ -275,7 +275,7 @@ INST(thumb32_MLS, "MLS", "111110110000nnnnaaaadd //INST(thumb32_SMMUL, "SMMUL", "111110110101----1111----000-----") //INST(thumb32_SMMLA, "SMMLA", "111110110101------------000-----") //INST(thumb32_SMMLS, "SMMLS", "111110110110------------000-----") -//INST(thumb32_USAD8, "USAD8", "111110110111----1111----0000----") +INST(thumb32_USAD8, "USAD8", "111110110111nnnn1111dddd0000mmmm") //INST(thumb32_USADA8, "USADA8", "111110110111------------0000----") // Long Multiply, Long Multiply Accumulate, and Divide diff --git a/src/frontend/A32/translate/impl/thumb32_multiply.cpp b/src/frontend/A32/translate/impl/thumb32_multiply.cpp index 51daa8fd..2a25be52 100644 --- a/src/frontend/A32/translate/impl/thumb32_multiply.cpp +++ b/src/frontend/A32/translate/impl/thumb32_multiply.cpp @@ -48,4 +48,17 @@ bool ThumbTranslatorVisitor::thumb32_MUL(Reg n, Reg d, Reg m) { return true; } +bool ThumbTranslatorVisitor::thumb32_USAD8(Reg n, Reg d, Reg m) { + if (d == Reg::PC || n == Reg::PC || m == Reg::PC) { + return UnpredictableInstruction(); + } + + const auto reg_m = ir.GetRegister(m); + const auto reg_n = ir.GetRegister(n); + const auto result = ir.PackedAbsDiffSumS8(reg_n, reg_m); + + ir.SetRegister(d, result); + return true; +} + } // namespace Dynarmic::A32 diff --git a/src/frontend/A32/translate/impl/translate_thumb.h b/src/frontend/A32/translate/impl/translate_thumb.h index e1cd29b6..9fbb3092 100644 --- a/src/frontend/A32/translate/impl/translate_thumb.h +++ b/src/frontend/A32/translate/impl/translate_thumb.h @@ -132,6 +132,7 @@ struct ThumbTranslatorVisitor final { bool thumb32_MLA(Reg n, Reg a, Reg d, Reg m); bool thumb32_MLS(Reg n, Reg a, Reg d, Reg m); bool thumb32_MUL(Reg n, Reg d, Reg m); + bool thumb32_USAD8(Reg n, Reg d, Reg m); // thumb32 parallel add/sub instructions bool thumb32_SADD8(Reg n, Reg d, Reg m);